AT32F421
Series Reference Manual
2022.11.11
Page 238
Rev 2.02
01: Write protection level 3, and the following bits are
write protected:
TMR1_BRK: DTC, BRKEN, BRKV and AOEN
TMR1_CTRL2: CxIOS and CxCIOS
10: Write protection level 2. The following bits and all bits
in level 3 are write protected:
TMR1_CCTRL: CxP and CxCP
TMR1_BRK: FCSODIS and FCSOEN
11: Write protection level 1. The following bits and all bits
in level 2 are write protected:
TMR1_CMx: C2OCTRL and C2OBEN
Note: When WPC>0, its content remains frozen until the
next system reset.
Bit 7: 0
DTC
0x00
rw
Dead-time configuration
This field defines the duration of the dead-time insertion.
The 3-bit MSB of DTC[7: 0] is used for function
selection:
0xx: DT = DTC [7: 0] * TDTS
10x: DT = (64+ DTC [5: 0]) * TDTS * 2
110: DT = (32+ DTC [4: 0]) * TDTS * 8
111: DT = (32+ DTC [4: 0]) * TDTS * 16
Note: Based on lock configuration, AOEN, BRKV, BRKEN, FCSODIS, FCSOEN and DTC[7:0] can all
be write protected. Thus it is necessary to configure write protection when writing to the
TMRx_BRK register for the first time.
14.4.4.16
TMR15 DMA control register (TMR15_DMACTRL)
Bit
Register
Reset value
Type
Description
Bit 15:13
Reserved
0x0
resd
Kept at its default value.
Bit 12:8
DTB
0x00
rw
DMA transfer bytes
This field defines the number of DMA transfers:
00000: 1 byte 00001: 2 bytes
00010: 3 bytes 00011: 4 bytes
...... ......
10000: 17 bytes 10001: 18 bytes
Bit 7:5
Reserved
0x0
resd
Kept at its default value.
Bit 4: 0
ADDR
0x00
rw
DMA transfer address offset
This field defines an offset starting from the address of the
TMR15_CTRL1 register:
00000: TMR15_CTRL1
00001: TMR15_CTRL2
00010: TMR15_STCTRL
......
14.4.4.17
TMR15 DMA data register (TMR15_DMADT)
Bit
Register
Reset value
Type
Description
Bit 15: 0
DMADT
0x0000
rw
DMA data register
A write/read operation to the DMADT register accesses
any TMR register located at the following address:
TMR15 peripheral a ADDR*4 to TMR15
peripheral a ADDR*4 + DTB*4