Instruction cycle timings
ARM DDI 0186A
Copyright © 2000 ARM Limited. All rights reserved.
11-3
11.2
When stall cycles do not occur
Before describing the various stall cycle scenarios, it is useful to consider the
circumstances where the ARM9E-S core can run within the ARM966E-S with no stall
cycles introduced by the system controller. When this is the case, the ARM966E-S is
running at peak efficiency and the instruction cycles exactly match those quoted in the
ARM9E-S Technical Reference Manual.
The fundamental requirement for no stall cycles is that the I-SRAM is enabled and the
necessary instructions have been previously programmed into it. Additionally, if the
D-SRAM is enabled, it can be accessed for reads without incurring a stall penalty, even
if the I-SRAM is being simultaneously accessed for an instruction fetch.
When a write is performed, the access can be zero stall if the write buffer is used and
there is space available. If the write is to the D-SRAM, the write is a single cycle in most
circumstances, and any store multiple to the D-SRAM can be executed as one write per
cycle. As long as these writes are not to the I-SRAM address space, instruction fetches
from the I-SRAM can be performed simultaneously without incurring a stall penalty.
To maximize performance, it is therefore desirable to ensure that frequently accessed
code is preloaded into the I-SRAM and that data accesses map to the D-SRAM address
space. It is also advisable to enable the write buffer and use bufferable areas of memory
where possible, when AHB writes are performed.
Note
If the data interface of the ARM9E-S core accesses the I-SRAM memory, in most cases
stall cycles are incurred. An example of where this type of access is unavoidable, is the
fetching of inline code literals from the I-SRAM.
Содержание ARM966E-S
Страница 6: ...Contents vi Copyright 2000 ARM Limited All rights reserved ARM DDI 0186A ...
Страница 20: ...Introduction 1 4 Copyright 2000 ARM Limited All rights reserved ARM DDI 0186A ...
Страница 48: ...Tightly coupled SRAM 4 12 Copyright 2000 ARM Limited All rights reserved ARM DDI 0186A ...
Страница 80: ...Bus Interface Unit 6 20 Copyright 2000 ARM Limited All rights reserved ARM DDI 0186A ...
Страница 118: ...Debug Support 8 26 Copyright 2000 ARM Limited All rights reserved ARM DDI 0186A ...
Страница 130: ...Test Support 10 8 Copyright 2000 ARM Limited All rights reserved ARM DDI 0186A ...
Страница 142: ...Instruction cycle timings 11 12 Copyright 2000 ARM Limited All rights reserved ARM DDI 0186A ...
Страница 158: ...Signal Descriptions A 16 Copyright 2000 ARM Limited All rights reserved ARM DDI 0186A ...
Страница 176: ...AC Parameters B 18 Copyright 2000 ARM Limited All rights reserved ARM DDI 0186A ...