UG-1828
Preliminary Technical Data
Rev. PrC | Page 96 of 338
SYNTHESIZER CONFIGURATION AND LO OPERATION
The ADRV9001 family devices employ four phase-locked loop (PLL) synthesizers: clock, RF (×2), and auxiliary. Each PLL is based on a
fractional-N architecture and consists of a common block made up of a reference clock divider, phase frequency detector, charge pump,
loop filter, feedback divider, and digital control block, and either a 1 or 4 core voltage-controlled oscillator (VCO). The VCO has a tuning
range of 6.5 GHz to 13 GHz. Each PLL drives its own local oscillator (LO) generator: RF LOGEN, aux LOGEN, and CLKGEN. The
output of the LOGEN block is a divided version of the VCO frequency. No external components are required to cover the entire
frequency range of the device. The reference frequency for the PLL is scaled from the reference clock applied to the device. Figure 90
illustrates synthesizer interconnection and clock/LO distribution block diagram.
Figure 90. Synthesizer Interconnection and Clock/LO Distribution Block Diagram
Each receiver channel can be used as an observation receiver (ORx) for transmitter channels as shown in Figure 91.
Figure 91. Synthesizer Interconnection and Clock/LO Distribution Diagram (Receiver Channels Configured as Observation Receivers for Transmitter Channels)
CLOCK SYNTHESIZER
The clock synthesizer is used to generate all the clocking signals necessary to run the device. The synthesizer uses a single core VCO
block. The reference frequency for the clock PLL is scaled from the device clock by the reference clock generator. Reconfiguration of the
clock synthesizer is typically not necessary after initialization. The most direct approach to configuration is to follow the recommended
programming sequence and use provided API functions to set the clock synthesizer to the desired mode of operation. The clock
generation block of the clock synthesizer provides clock signals for the high speed digital clock, receiver ADC sample and interface
clocks, transmitter DAC sample and interface clocks, and LVDS interface clocks.
RF SYNTHESIZER
The device contains two RF PLLs. Each RF PLL uses the PLL block common to all synthesizers in the device and employs a 4 core VCO
block which provides a 6 dB phase noise improvement over the single core VCO. As with the other synthesizers in the device, the
reference for RF PLL 1 and RF PLL 2 are sourced from the reference generation block of the device. The RF PLLs are also fractional-N
architectures with a programmable modulus. The default modulus of 8,388,473 is programmed to provide an exact frequency on at least a
5 kHz raster using certain reference clocks which are integer multiples of 38.40 Hz. The RF LO frequency is derived by dividing down the
VCO output in the LOGEN block. The tunable range of the RF LO is 30 MHz to 6000 MHz.
A switching network is implemented in the device to provide flexibility in LO assignment for the two RF LO sources. The switching
network is shown in Figure 92 and Figure 93.
CLOCK
SYNTHESIZER
RF 1
SYNTHESIZER
RF 2
SYNTHESIZER
AUXILLARY
SYNTHESIZER
BB CLOCK
GENERATOR
RF LO1
GENERATOR
RF LO2
GENERATOR
AUX LO
GENERATOR
DIGITAL, ADCs,
DACs, LVDS
TX1
RX2
RX1
TX2
CALIBRATION
CLK PLL
REF
CLK PLL1
REF
CLK PLL2
REF
REFCLK
GEN
REF CLK IN±
AUX PLL
REF
24159-
074
CLOCK
SYNTHESIZER
RF1
SYNTHESIZER
RF2
SYNTHESIZER
AUXILLARY
SYNTHESIZER
BB CLOCK
GENERATOR
RF LO1
GENERATOR
RF LO2
GENERATOR
AUX LO
GENERATOR
DIGITAL, ADCs,
DACs, LVDS
TX1
RX2/ORX2
RX1/ORX1
TX2
CALIBRATION
CLK PLL
REF
CLK PLL1
REF
CLK PLL2
REF
REFCLK
GEN
REF CLK IN±
AUX PLL
REF
24159-
075
