Preliminary Technical Data
UG-1828
Rev. PrC | Page 191 of 338
POWER SAVING AND MONITOR MODE
ADRV9001 is a high-performance integrated transceiver with low power considerations. To accommodate different user cases,
ADRV9001 provides flexibility for users to trade-off between power consumption and performance with some static configuration
options, such as:
•
Clock PLL option of high performance and low power;
•
Clock PLL power option of high, medium and low;
•
ADC option of high performance or low power;
•
ADC clock rate option of high, medium and low;
•
RF PLL LOGEN optimization option of best phase noise and best power consumption;
•
RF PLL power option of high, medium and low;
•
ARM clock rate option of divided by 1, 2, 4
These static options are chosen and configured in chip initialization stage and are not allowed to dynamically change except the ADC
option, high performance ADC, and low power ADC can be dynamically switched after chip has been initialized. Users can refer the
relative sections for above options detail in the User Guide.
For TDD applications, ADRV9001 defines different power saving modes to meet the power saving requirement in various user cases.
Some standards like DMR (Digital Mobile Radio) require the radio enter periodical sleep and carrier detection cycles in order to save
power (Monitor Mode) when radio is not in use. ADRV9001 has dedicated hardware to meet this Monitor Mode requirement, and
ADRV9001 software adds additionally static and dynamic power saving schemes in order to extend the power saving feature to a broader
market beyond DMR.
ADRV9001 defines five extra power down modes that provides from low to high power saving but short to long recovery time, details will
be introduced in the following section.
Three power saving schemes are designed for different power saving applications.
•
Temporarily powering up/down the unused Tx/Rx channel in Calibrated state
•
Dynamic interframe power saving is running automatically during all regular TDD TX/RX operations. DGPIO pins could be
configured to support additional power savings. All configurations can be set by API via fast messages on the fly. Power saving
software will smartly handle powering up/down HW components based on PLL mapping and selected power saving mode. There are
two power saving choices in interframe operations:
•
Channel power saving. This is to power down a channel (both TX and RX) based on power down mode 0-2.
•
System power saving. This is to power down the whole chip by power down mode 3-5
•
Monitor Mode. This can allow baseband processor move into sleep state after it configures and moves ADRV9001 into Monitor
mode, ADRV9001 software will control the dedicated hardware and timers for periodical sleeping and detecting. Only power down
modes 3-5 are allowed in Monitor Mode.
Users can choose proper power down modes and power saving schemes according to their application scenarios. The following sections
explain the detail power saving schemes.
POWER-DOWN MODES
Power down modes are defined to dynamically power down and up different level of ADRV9001 components. Five extra power down
modes are defined from low power saving but short recover time to high power saving but long recover time as shown in Table 78. Each
higher power down mode would power down additional components than the lower mode, power down mode 3 is the exception.
Table 78. Power-Down Modes and Related Power-Down Components
Power Down Modes
0 (default)
1
2
3
4
5
Components
TX
Analog and Digital Data Path
x
x
x
x
x
x
TX Internal PLLs
x
x
x
x
x
TX LDOs
x
x
x
RX
Analog and Digital Data Path
x
x
x
x
x
x
RX Internal PLLs
x
x
x
x
x
RX LDOs
x
x
x
System
CLK PLL
x
x
x
Converter and CLKPLL LDOs
x
x
ARM (+ memories)
x
Approximate Power-Up Time (μs)
1,3
DEV_CLK = 30Mhz
4.5
350
500
250
650
3200
