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44409
Rev.
1.70
October 10
AMD SP5100 Databook
Testability
79
Table 14-4: Truth Table for an XOR Chain
Test Vector
number
Input Pin G Input Pin F
Input Pin E Input Pin D Input Pin C Input Pin B Output Pin A
1
0
0
0
0
0
0
1
2
1
0
0
0
0
0
0
3
1
1
0
0
0
0
1
4
1
1
1
0
0
0
0
5
1
1
1
1
0
0
1
6
1
1
1
1
1
0
0
7
1
1
1
1
1
1
1
14.2.2 Description of the SP5100 XOR Chain
During XOR Chain Test Mode, most of the chip pads on the SP5100 are connected together
using XOR gates as shown in Figure 14-3. The first input of the chain is connected to a logic level
high (internal connection), and all pads (listed in Table 14-5) are configured as inputs except for
the last pad in the chain, which is configured as an output.
KBRST#/GEVENT1#
is the start of the
chain and
SERIRQ
is the end of the chain. Table 14-5 lists all pads that are on the SP5100 XOR
chain, as well as and their order of connection. Pads are chained together in the shown order,
i.e., pad number 1 is the first pad on the XOR chain, pad number 2 the second, and so on.
1 ( Tie high Internal to Asic)
pin 1
AD6/ROMA12
pin 2
pin 3
pin N
Frame#
XOR out
FANOUT0/ GPIO3
Figure 14-3: On-chip XOR Chain connectivity
Table 14-5: List of Pins on the SP5100 XOR Chain and the Order of Connection
XOR #
Pin Name
1
KBRST#/GEVENT1#
2
GA20IN/GEVENT0#
3
NB_PWRGD
4
SATA_ACT#/GPIO67
5
LDRQ1#/GNT5#/GPIO68
6
AD20
7
CBE2#
8
REQ2#
9
BMREQ#/REQ5#/GPIO65
10
REQ4#/GPIO71
11
GNT3#/GPIO72
12
CLKRUN#
13
REQ3#/GPIO70
XOR #
Pin Name
14
GNT4#/GPIO73
15
INTF#/GPIO34
16
REQ1#
17
GNT1#
18
INTE#/GPIO33
19
INTH#/GPIO36
20
GNT0#
21
INTG#/GPIO35
22
AD31
23
GNT2#
24
REQ0#
25
AD29
26
AD30