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44409
Rev.
1.70
October 10
AMD SP5100 Databook
Signal Description
33
7 Signal Description
7.1
CPU Interface
Pin name
Type
Voltage
Functional Description
LDT_PG
OD
S5_3.3V
LDT Power Good
LDT_RST#
OD
S5_3.3V
LDT Reset#
LDT Reset#: Reset signal to the CPU.
Assertion of LDT_RST# causes the CPU to transition into a low power
state and to de-assert MEMCLKEA/B and assert MEMREST_L.
Assertion of LDT_RST# takes place sometime after SB PWR_GOOD
has been de-asserted.
De-assertion of LDT_RST# allows MEMRESET_L to be de-asserted
and MEMCLK to be enabled. De-assertion of LDT_RST# takes place
sometime after SB PWR_GOOD has been asserted.
LDT_STP#
OD
S5_3.3V
Assertion of LDTSTOP# on the CPU causes it to enter C3, or
S1/S2/S3/S4/S5. Assertion takes place: (a) for S1/S2/S3/S4/S5: after
SUS_STAT# is asserted; (b) for C3: after the STPGNT message is
received by the system.
De-assertion of LDTSTOP_L causes the CPU to return to C0 or S0
state. De-assertion takes place following a wake-up event:
(a) in S1: at an interval (programmed by an SB register) after de-
assertion of CPU_STP#;
(b) in S2: after SLP_S2 is de-asserted;
(c) in S3/S4/S5: after SB PWR_GOOD is asserted;
(d) in C3: at an interval (programmed by an SB register)
Starting with RS78x, NB will control the LDT_STP# during C state.
PROCHOT#
I
0.8-V
threshold,
S5_3.3V
domain
Processor Hot: Similar to TALERT#. When it is asserted, it can
generate SCI or SMI to OS/BIOS.
7.2
LPC Interface
Pin Name
Type
Voltage
Functional Description
GA20IN
I
3.3 V
A20 Gate Input from SIO
KBRST#
I
3.3 V
Keyboard reset#
LAD[3:0]
I/O
S5_3.3 V
Multiplexed Command/Address/Data [3:0]
LPCCLK0
O
S5_3.3 V
LPCCLK 0 (See
Note
)
LPCCLK1
O
S5_3.3 V
LPCCLK 1 (See
Note
)
LFRAME#
O
S5_3.3 V
Frame. Indicates start of a new cycle or termination of
broken cycle.
LDRQ0#
I
S5_3.3 V
Encoded DMA/Bus Master Request 0
LDRQ1#/GNT5#/
GPIO68
I/O
3.3 V
Encoded DMA/Bus Master Request 1 / PCI bus Grant 5
from SP5100 / GPIO 68
LPC_SMI#/EXTEVNT1#
I
S5_3.3 V
LPC SMI / External Event 1
SERIRQ
I/O
3.3 V
Serial IRQ