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AMD SP5100 Databook
44409 Rev. 1.70 October 10
48
Signal Description
Pin Name
Type
Voltage
Functional Description
PCIE_RCLKN/
NB_LNK_CLKN
I/O
CKVDD_1.2
Negative phase 100-MHz reference clock (negative) for
SP5100.
GPP_CLK[3:0]P
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
GPP_CLK[3:0]N
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
CLK_REQ0#/SATA_IS3#/
GPIO0
I
3.3 V
PCI Express
®
clock request 0
CLK_REQ1#/SATA_IS4#/
FANOUT3/GPIO39
I
3.3 V
PCI Express clock request 1
CLK_REQ2#/SATA_IS5#/
FANIN3/GPIO40
I
3.3 V
PCI Express clock request 2
CLK_REQ3#/SATA_IS1#/
GPIO6
I
3.3 V
PCI Express clock request 3
25M_48M_66M_OSC
O
S5_VDD33
14 MHz reference clock input
NB_DISP_CLKP
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
NB_DISP_CLKN
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
CPU_HT_CLKP
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
CPU_HT_CLKN
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
NB_HT_CLKP
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
NB_HT_CLKN
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
SLT_GFX_CLKP
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
SLT_GFX_CLKN
O
CKVDD_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
USBCLK/
14M_25M_48M_OSC
I/O
S5_3.3V
48-MHz input clock used for USB
RSMRST#
I
S5_3.3V
Resume Reset from Motherboard –
Assertion of RSMRST# resets all SP5100 registers to their
default values. It also causes all reset signals originating
from the SP5100 (A_RST#, PCIRST#, LDT_RST#,
AZ_RST#, AC_RST#) to be issued. RSRMT# should be
asserted when system power is being applied. Type-I straps
are captured on the rising edge of RSRMT# during its de-
assertion. RSMRST# should be de-asserted sometime after
S5 power is up, and should stay de-asserted until system
power is removed.
SYS_RESET#/GPM7#
I/O
S5_3.3V
System Reset / GPM 7
System Reset: Signal coming from the power button circuit
signaling a reset for the system. On receiving the signal, the
SP5100 asserts all reset signals that originate from the
SP5100 including: A_RST#, PCIRST#, LDT_RST#,
AZ_RST#, and AC_RST#; it also resets all SP5100
registers to their default values.
LAN_RST#/GPIO13
I/O
3.3 V
Early version of A_RST#; meant for resetting LAN MAC.
This signal is early to allow LAN to load its LON first
ROM_RST#/GPIO14
I/O
S5_3.3V
Early version of A_RST#, meant for resetting the system
BIOS flash