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44409
Rev.
1.70
October 10
AMD SP5100 Databook
Signal Description
35
Pin Name
Type
Voltage
Functional Description
PCIRST#
O
3.3 V (5-V Tolerance)
Hardware Reset for PCI Slots
Assertion: (a) at power on, (b) sometime after
CPU_STP#’s assertion in S0, (c) after the system has
transitioned into S4/S5.
De-assertion: sometime after SB PWR_GOOD is asserted
during power on or during a transition from S4/S5 to S0.
PERR#
I/O
3.3 V (5-V Tolerance)
Parity Error: reports data parity errors during all PCI
transactions, except in a special cycle.
REQ#[2:0]
I
3.3 V (5-V Tolerance)
Request [2:0] Input: indicates that the agent desires use of
the bus.
REQ3#/GPIO70
I
3.3 V (5-V Tolerance) PCI Request 3 Input / GPIO 70
REQ4#/GPIO71
I
3.3 V (5-V Tolerance) PCI Request 4 Input / GPIO 71
SERR#
I/OD
3.3 V (5-V Tolerance)
System Error: for reporting address parity errors and data
parity errors on the special cycle command, or any other
system error where the result will be catastrophic.
STOP#
I/O
3.3 V (5-V Tolerance)
Stop: indicates the current target is requesting the master
to stop the current transaction
TRDY#
I/O
3.3 V (5-V Tolerance)
Target Ready
Target Ready: indicates the target agent’s ability to
complete the current data phase of the transaction.
7.5
USB Interface
Pin Name
Type
Voltage
Functional Description
USB_HSD[11:0]P
I/O
AVDD_TX
USB 2.0 Port 11 ~ 0 Positive I/O (See
Note 1
)
USB_HSD[11:0]N
I/O
AVDD_TX
USB 2.0 Port 11 ~ 0 Negative I/O (See
Note 1
)
USB_FSD[13:12]P
I/O
S5_3.3V
USB 1.1 port 13:12 (full/low speed) Positive I/O (See
Note 2
)
USB_FSD[13:12]N
I/O
S5_3.3V
USB 1.1 port 13:12 (full/low speed) Negative I/O (See
Note 2
)
USBCLK/
14M_25M_48M_OSC
I
S5_3.3V
48-MHz input clock used for USB
USB_RCOMP
I
AVDDC
Compensating resistors input
USB_OC[5:0[#/
GPM[5:0]#
I/O
S5_3.3V
USB Over Current [5:0] / GPM [5:0]
USB_OC4# is also multiplexed as IR_RX0
USB_OC6#/IR_TX1/
GEVENT6#
I/O
S5_3.3V
USB Over Current 5 / General Event 6
Notes:
(1) The USB_HSD[11:0]P and USB_HSD[11:0]N signals are used for connecting internal or external USB
devices via USB Port connectors. These ports are handled by users and are subject directly to ESD events
to either the connector, the device, or to the pins themselves. The USB_HSDP and USB_HSDN signals that
may be exposed to the user through an USB port connection must have ESD protection.
(2) The USB_FSD[13:12]P and USB _FSD[13:12]N signals are used only for connecting to internal devices.
They support only full or low, but not high speed devices.
7.6
PATA 66/100/133
Note:
The SP5100 does not support the flash controller function. The flash controller should be disabled
by BIOS, and the interface can only be used for IDE function (or as GPIOs, in case of the IDE data bus
bits). Portions of the pin names below that imply flash controller function should be ignored. See the
SP5100 Schematic Review Checklist
for how to terminate these signals if they are not used.