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44409
Rev.
1.70
October 10
AMD SP5100 Databook
Signal Description
47
disabled. If not used, pins on this interface should be terminated in the manner described in the
AMD
SP5100 Schematic Review Checklist.
The SMBUS is independent of the IMC controller. It is usable even when the IMC is disabled. When the
IMC is enabled, the SMBUS controller is shared between the host and the IMC. The IMC can control the
SMBus and the IMC interfaces if they are not used by the host, and that is achieved through software.
Pin Name
Type
Voltage
Functional Description
IMC_GPIO[1:0]
I/O
S5_3.3V
(5-V Tolerance)
IMC GPIO [1:0]
SPI_CS2#/IMC_GPIO2
I/O
S5_3.3V
2nd SPI Chip Select# / IMC GPIO 2
IDE_RST#/F_RST#/
IMC_GPO3
I/O
S5_3.3V
(5-V Tolerance)
IDE Reset / IMC GPO 3
IMC_GPIO [7:4]
I/O
S5_3.3V
(5-V Tolerance)
IMC GPIO [7:4]
IMC_GPIO [9:8]
I/O
S5_3.3V
IMC GPIO [9:8]
IMC_PWM0/IMC_GPIO10
I/O
S5_3.3V
IMC PWM 0 / IMC GPIO 10
SCL2/IMC_GPIO11
I/O
S5_3.3V
(5-V Tolerance)
SMBus Clk 2 / IMC GPIO 11
SDA2/IMC_GPIO12
I/O
S5_3.3V
(5-V Tolerance)
SMBus Data 2 / IMC GPIO 12
SCL3_LV/IMC_GPIO13
I/O
0.8-V threshold,
S5_3.3V domain
IMC GPIO 13/ SMBus Clk 3 for CPU temp status
SDA3_LV/IMC_GPIO14
I/O
0.8-V threshold,
S5_3.3V domain
IMC GPIO 14/ SMBus Data 3 for CPU temp status
IMC_PWM1/IMC_GPIO15
I/O
S5_3.3V
IMC PWM 1* / IMC GPIO 15
IMC_PWM2/IMC_GPO16
I/O
S5_3.3V
(5-V Tolerance)
IMC PWM 2* / IMC GPIO 16
IMC_PWM3/IMC_GPO17
I/O
S5_3.3V
(5-V Tolerance)
IMC PWM 3* / IMC GPIO 17
IMC_GPIO[41:18]
I/O
S5_3.3V
IMC GPIO [41:18]
*Note:
The IMC power management controller is NOT supported by the SP5100. The pins can only be used as
GPIOs.
7.17 Reset / Clocks / ATE
Note:
Clock generator function is NOT SUPPORTED by the SP5100.
Pin Name
Type
Voltage
Functional Description
A_RST#
O
S5_3.3V
PCI Host Bus Reset. Asserted during transition to S3/S4/S5
to reset all devices in the SP5100 or connected to it, except
the ACPI logic in the SP5100
14M_X1
I
AVDDCK_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
14M_X2
O
AVDDCK_1.2
Reserved. See
SP5100 Schematic Review Checklist
for
how to connect.
PCIE_RCLKP/
NB_LNK_CLKP
I/O
CKVDD_1.2
Positive phase 100-MHz reference clock (positive) for
SP5100.