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AMD SP5100 Databook
44409 Rev. 1.70 October 10
18
SP5100 Power on Sequence and Timing
Note 10:
The following figure shows the timing of SB PWR_GOOD de-asserted to RSMRST#
de-asserted during a power down sequence. However, this timing only applies to S0 to G3
state transition, because G3 state is where both signals are inactivated.
SB PWR_GOOD
T14
RSMRST#
S0 to G3
Figure 3-4: Timing for SB PWR_GOOD De-asserted to RSMRST# De-asserted
Note 11:
On first power up, G3
S5, or after RSMRST# assertion, the LDT_STP# will be asserted
with CPU_VDDIO power. On subsequent power up, S5
S0, the timing on T9B will apply.
CPU_VDDIO
LDT_STP#
SB PWRGOOD
Timing is system
depended
Figure 3-5: Timing for LDT_STP# assertion on first power up (G3
S5)