AMD Am186 ES, Руководство пользователя, Страница: 44 / 192

System Overview 3-12
Unlike the UCS and LCS chip selects, the PCS outputs assert with the
multiplexed AD address bus. Note also that each peripheral chip select
asserts over a 256-byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and 80C188
microcontrollers.
A2—When the EX bit in the MCS and PCS auxiliary register is 0, this
pin supplies an internally latched address bit 2 to the system. During a
bus hold condition, A2 retains its previously latched value.
PIO31–PIO0 (Shared)
Programmable I/O Pins (input/output, asynchronous, open-drain)
The Am186ES and Am188ES microcontrollers provide 32 individually
programmable I/O pins. Each PIO can be programmed with the
following attributes: PIO function (enabled/disabled), direction (input/
output), and weak pullup or pulldown. The pins that are multiplexed with
PIO31–PIO0 are listed in Table 3-1 and Table 3-2.
After power-on reset, the PIO pins default to various configurations. The
column titled Power-On Reset Status in Table 3-1 and Table 3-2 lists the
defaults for the PIOs. Most of the PIO pins are configured as PIO inputs
with pullup after power-on reset. The system initialization code must
reconfigure any PIO pins as required.
The A19–A17 address pins default to normal operation on power-on
reset, allowing the processor to correctly begin fetching instructions at
the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default
to normal operation on power-on reset.