AMD Am186 ES, Руководство пользователя, Страница: 34 / 192

System Overview 3-2
AO15–AO8 Address-Only Bus, Am188ES Microcontroller
(output, three-state, synchronous, level-sensitive)
AO15–AO8—On the Am188ES microcontroller, the address-only bus
(AO15–AO8) contains valid high-order address bits from bus cycles t
1
–
t
4
. When address generation is disabled (AD = 1), the address on this
bus is not valid during t
1
. These outputs are floated during a bus hold
or reset.
On the Am188ES microcontroller, AO15–AO8 combine with AD7–AD0
to form a complete multiplexed address bus while AD7–AD0 is the 8-
bit data bus.
AD7–AD0 Address and Data Bus
(input/output, three-state, synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or I/O addresses,
as well as data, to the system. This bus supplies the low-order 8 bits of
an address to the system during the first period of a bus cycle (t
1
), and
it supplies data to the system during the remaining periods of that cycle
(t
2
, t
3
, and t
4
). In 8-bit mode on the Am188ES microcontroller, AD7–
AD0 supplies the data.
The address phase of these pins can be disabled. See the ADEN
description with the BHE/ADEN pin. When WLB is not asserted, these
pins are three-stated during t
2
, t
3
, and t
4.
During a bus hold or reset condition, the address and data bus is in a
high-impedance state.
During a power-on reset, the address and data bus pins (AD15–AD0
for the 186, AO15–AO8 and AD7–AD0 for the 188) can also be used to
load system configuration information into the internal reset
configuration register.
ALE Address Latch Enable (output, synchronous)
This pin indicates to the system that an address appears on the address
and data bus (AD15–AD0 for the 186 or AO15–AO8 and AD7–AD0 for
the 188). The address is guaranteed to be valid on the trailing edge of
ALE. This pin is three-stated during ONCE mode. This pin is not three-
stated during a bus hold or reset.
ARDY Asynchronous Ready (input, asynchronous, level-sensitive)
This pin is a true asynchronous ready that indicates to the
microcontroller that the addressed memory space or I/O device will
complete a data transfer. The ARDY pin is asynchronous to CLKOUTA
and is active High. To guarantee the number of wait states inserted,
ARDY or SRDY must be synchronized to CLKOUTA. If the falling edge
of ARDY is not synchronized to CLKOUTA as specified, an additional
clock period may be added.
To always assert the ready condition to the microcontroller, tie ARDY
High. If the system does not use ARDY, tie the pin Low to yield control
to SRDY.