Altera EP2AGX125, Руководство по эксплуатации устройства

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Chapter 5: Clock Networks and PLLs in Arria II Devices 5–37
PLLs in Arria II Devices
December 2010 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration
Arria II PLLs support a fully configurable clock switchover capability. Figure 5–30
shows the block diagram of the switchover circuit built into the PLL. When the
current reference clock is not present, the clock sense block automatically switches to
the backup clock for PLL reference. The clock switchover circuit also sends out three
status signals—
clkbad[0]
,
clkbad[1]
, and
activeclock
—from the PLL to implement
a custom switchover circuit in the logic array. You can select a clock source as the
backup clock by connecting it to the
inclk1
port of the PLL in your design.
Automatic Clock Switchover Mode
Use the switchover circuitry to automatically switch between
inclk0
and
inclk1
when the current reference clock to the PLL stops toggling. For example, in
applications that require a redundant clock with the same frequency as the reference
clock, the switchover state machine generates a signal (
clksw
) that controls the
multiplexer select input, as shown in Figure 5–30 . In this case,
inclk1
becomes the
reference clock for the PLL. When you use the automatic switchover mode, you can
switch back and forth between the
inclk0
and
inclk1
clocks any number of times,
when one of the two clocks fails and the other clock is available.
When you use the automatic clock switchover mode, the following requirements
must be satisfied:
■ Both clock inputs must be running.
■ The period of the two clock inputs can differ by no more than 100% (2×).
If the current clock input stops toggling while the other clock is also not toggling,
switchover is not initiated and the
clkbad[0:1]
signals are not valid. Also, if both
clock inputs are not the same frequency, but their period difference is 100%, the clock
sense block detects when a clock stops toggling, but the PLL may lose lock after the
switchover is completed and requires time to relock.
1
Altera recommends resetting the PLL with the
areset
signal to maintain the phase
relationships between the PLL input and output clocks when you use clock
switchover.
Figure 5–30. Automatic Clock Switchover Circuit Block Diagram for Arria II Devices
Switchover
State
Machine
Clock
Sense
n Counter
PFD
clkswitch
activeclock
clkbad1
clkbad0
muxout
inclk0
inclk1
r efclk
fbclk
clk s w
Clock Switch
Control Logic