Altera EP2AGX125, Руководство по эксплуатации устройства

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5–14 Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration December 2010 Altera Corporation
Table 5–12 lists the mapping between the input clock pins, PLL counter outputs, and
clock control block inputs.
1
When combining the PLL outputs and clock pins in the same clock control block,
ensure that these clock sources are implemented on the same side of the device.
For all possible legal
inclk
sources for each GCLK and RCLK network, refer to
Table 5–2 on page 5–9 through Table 5–10 on page 5–12 .
You can statically control the clock source selection for the RCLK select block with
configuration bit settings in the configuration file generated by the Quartus II
software.
You can power down the Arria II clock networks both statically and dynamically.
When a clock network is powered down, all the logic fed by the clock network is in an
off-state, thereby reducing the overall power consumption of the device. The unused
GCLK and RCLK networks are automatically powered down through configuration
bit settings in the configuration file generated by the Quartus II software. The
dynamic clock enable or disable feature allows the internal logic to control power-up
or power-down synchronously on GCLK and RCLK networks. This function is
independent of the PLL and is applied directly on the clock network, as shown in
Figure 5–8 through Figure 5–10 .
You can set the input clock sources and the
clkena
signals for the GCLK and RCLK
clock network multiplexers through the Quartus II software with the ALTCLKCTRL
megafunction. You can also enable or disable the dedicated external clock output pins
with the ALTCLKCTRL megafunction.
1
When you use the ALTCLKCTRL megafunction to implement dynamic clock source
selection in Arria II devices, the inputs from the clock pins, except for the left side of
the Arria II GX device, feed the
inclk[0..1]
ports of the multiplexer, and the PLL
outputs feed the
inclk[2..3]
ports. You can choose from among these inputs with the
CLKSELECT[1..0]
signal. For the connections between the PLL counter outputs to the
clock control block, refer to Table 5–12 on page 5–14 .
Table 5–12. Mapping Between Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs for Arria II
Devices
Clock Control Block Inputs Description
inclk[0]
,
inclk[1]
(1) Can be fed by any of the four dedicated clock pins on the same side.
inclk[2]
■
For Arria II GX device—can be fed by PLL counters
C0
and
C2
from the two corner PLLs
on the same side.
■
For Arria II GZ device—can be fed by PLL counters C0 and C2 from the two center PLLs
on the same side.
inclk[3]
■
For Arria II GX device—can be fed by PLL counters
C1
and
C3
from the two corner PLLs
on the same side.
■
For Arria II GZ device—can be fed by PLL counters
C1
and
C3
from the two center PLLs
on the same side.
Note to Table 5–12 :
(1) The left side of the Arria II GX device only allows PLL counter outputs as the dynamic clock source selection to the GCLK network. Therefore,
inclk[0]
can be fed by PLL counters
C4
or
C6
, while
inclk[1]
can only be fed by PLL counter
C5
.