Chapter 5: Clock Networks and PLLs in Arria II Devices
5–11
Clock Networks in Arria II Devices
December 2010
Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Clock Input Connections to PLLs
and
list dedicated clock input pin connectivity to Arria II PLLs.
Clock Output Connections
PLLs in Arria II GX devices can drive up to 24 RCLK networks and eight GCLK
networks, while PLLs in Arria II GZ devices can drive up to 20 RCLK networks and
four GCLK networks. The Quartus
®
II software automatically assigns PLL clock
outputs to RCLK or GCLK networks.
Table 5–6. PLLs and PLL Clock Pin Drivers for Arria II GX Devices
Dedicated Clock Input Pin CLK (p/n Pins)
PLL Number
1
2
3
4
5
6
CLK[4..7]
—
—
v
v
—
—
CLK[8..11]
—
v
v
—
v
v
CLK[12..15]
v
v
—
—
—
—
Note to
(1)
PLL_5
and
PLL_6
are connected directly to
CLK[8..11]
.
PLL_1
,
PLL_2
,
PLL_3
and
PLL_4
are driven by the clock input pins through a 4:1
multiplexer.
Table 5–7. PLLs and PLL Clock Pin Drivers for Arria II GZ Devices
,
Dedicated Clock Input Pin CLK
(p/n Pins)
PLL Number
L2
L3
B1
B2
R2
R3
T1
T2
CLK[0..3]
v
v
—
—
—
—
—
—
CLK[4..7]
—
—
v
v
—
—
—
—
CLK[8..11]
—
—
—
—
v
v
—
—
CLK[12..15]
—
—
—
—
—
—
v
v
(1) For single-ended clock inputs, only the
CLK
<#>
p
pin has a dedicated connection to the PLL. If you use the
CLK
<#>
n
pin, a GCLK is used.
(2) For the availability of the clock input pins in each device density, refer to the “Arria II Device Pin-Out Files” section of the