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Chapter 5: Troubleshooting
configured in bypass mode (PLL is not used), then verifies that the PLL can be
enabled and used to generate additional clock frequencies.
Inter-chip Resource Bus Test.
The purpose of this test is to verify that the
Inter-chip Resource lines (ICRs) can be driven as outputs and received as inputs
by each chip in the module. The Inter-chip Resource lines (ICRs) are the open
drain signals external to the Analysis chips that combine the precombiner
outputs from each chip for input to the postcombiners. These are the signals that
are connected between same boards in a module using the flex circuit cabling.
The signals are open drain outputs to allow the wire ANDing/ORing between the
chips. The same pins are used for both output and input of the ICR signals.
Inter-module Flag Bits Test.
The purpose of this test is to verify that the four
Inter-module Flag Bit Output lines can be driven out from the master chip in the
module and received by each chip in the module. In SVY frames eight flag signals
available on the backplane. System software dedicates four of these as flag bit
outputs from the modules and four as flag bit inputs. The 16753/4/5/6 module
drives the four flag outputs from the master chip and can receive the four flag
inputs on any chip. Instruments can use these flags to communicate between
modules (or within the same module if desired).
Global and Local Arm Lines.
The purpose of this test is to verify that the
Local Arm signal can be received by each Analysis chip on the master board, and
the Global Arm signal can be driven by each chip on the master board and
received by all chips in the module (master and slave).
LA Chip Calibrations Test.
The purpose of this test is to verify that each
analysis chip in the module is able to successfully complete self-calibration.
The PV test works by configuring the module in various configurations and calling
the real hardware driver code's calibration routines. The results of the calibration
are then checked to see if cal passed or failed.
Comparator Calibrations Test.
The purpose of this test is to verify that each
of the comparator one-time calibrations can successfully be performed. This
verifies that all of the calibration circuitry and components are within the
tolerance limits required for proper calibration. This test is executed only if all
probes are detached.
Timing Zoom Memory BIST (Built-In Self Test).
This test verifies that the
timing zoom SRAMs embedded in the analysis chips is functional. The test uses
the built-in hardware self test for the SRAMs.
Timing Zoom Memory Addr/Data Test.
This test verifies connectivity of
components within the analysis chip. It verifies that the address, data, and clock
lines of the timing zoom circuitry is correct.
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