abaco systems SBC329 3U VPX, Справочник по аппаратуре

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Publication No. SBC329-HRM/1 FPGA Registers 81
LPC I/O Port Description Access LPC I/O Port Description Access
0x6BD COM Port RS485 Auto Direction Control Read/Write 0x6C8 XMC Status Read only
0x6BE COM Port Loopback Enable Read/Write 0x6CA Backplane Status Read only
0x6BF SSD Erase Control Read/Write 0x6CB SSD Status Read only
0x6C0 SSD Cache Flush Control Read/Write 0x6CC Write Protection Status Read only
0x6C1 VPX Control Read/Write 0x6CD Board Jumper Link Status Read only
0x6C6 Scratchpad Read/Write 0x6CE Boot Location Status Read only
0x6C7 Test Read only
Any LPC I/O ports not shown in the table above are reserved.
C&S = Control and Status.
CAUTION
These registers are intended to be accessed only by proprietary driver software.
Other access to these registers could cause the SBC329 to malfunction.
NOTE
The descriptions shown below are for reference only, and are subject to change.
6.1 Board ID Register (0x600)
This returns the value 0x90 to identify the SBC329.
6.2 Board Revision Register (0x601)
Bits Description Default
7 to 4 Major assembly revision (artwork):
0x1 = Rev 1, 0x2 = Rev 2, etc. N/A
3 to 0 Minor revision (hardware build state revision):
0x0 = Rev A, 0x1 = Rev B N/A
6.3 FPGA Revision Register (0x60B)
Bits Description Default
7 to 0 Revision of FPGA code:
0x1 = Rev 1, 0x2 = Rev 2, etc. N/A