Publication No. SBC329-HRM/1
Functional Description 49
5.2.2
Mobile Intel CM238 Chipset (PCH)
The following features of the PCH are implemented on the SBC329:
Two PCIe Gen2 x4 root ports
SATA host controller supporting three ports at 6 Gbits/second (Gen3)
LPC interface
SPI interface for Boot Flash
APIC interrupt controller
Two USB XHCI controllers supporting two USB2.0 and one USB3.0 ports
RTC
–
Motorola MC146818B-compatible
Enhanced Power Management
SMBus 2.0 (I
2
C)
Integrated Clock controller
5.2.3
Processor Debug Port
The SBC329 provides access to the debug port on the processor via the TAC. This
includes a Samtec 60-way SH-030-01-L-D-A connector in accordance with Intel
recommendations, and conforms to the Intel eXtended Debug Port (XDP) standard
pin-out, allowing probes from various vendors to be used.
A TAC is available if required (part number SBC328TST-11). Contact Abaco for
ordering information.
5.3 Memory
5.3.1
SDRAM
The SBC329 provides two ranks of DDR4 SDRAM with ECC. The following table
shows the RAM configuration:
Table 5-2 SDRAM Configuration
Total RAM
(GB)
Total Number
of Devices
Device Density
(Gbit)
Number of
Ranks
16
18
8
2
The SDRAM operates at an interface speed of 2400 megatransfers/second (JEDEC
PC4-19200), which provides a maximum theoretical bandwidth of 19200 MB/second.
NOTE
The actual RAM configuration fitted to the SBC329 may change as different RAM density devices
become available. Check with Abaco for latest memory capability.
