Publication No. SBC329-HRM/1
FPGA Registers 91
6.15 VPX GDISC1 Registers
The GDISC1 pin to register bit mapping for the following registers is as follows:
Bits
Read/Write Description
7
Read/Write GDISC1
6 to 0
Read only
Reserved
6.15.1
VPX GDISC1 Out Register (0x688)
The value of this register is driven onto the GDISC1 pin when the direction mode is
set to output. The default is 0x00.
6.15.2
VPX GDISC1 In Register (0x689)
This returns the status of the GDISC1 pin, regardless of the direction mode. The
default is 0x00.
6.15.3
VPX GDISC1 Direction Register (0x68A)
Bit 7 shows the direction (output or input) of the GDISC1 pin, as follows:
1 = Output
0 = Input (default)
6.15.4
VPX GDISC1 Interrupt Enable Register (0x68B)
Bit 7 enables interrupts for the GDISC1 pin, as follows:
1 =Interrupt enabled
0 = Interrupt masked (default)
6.15.5
VPX GDISC1 Level/Edge Register (0x68C)
Bit 7 sets the interrupt detection sensitivity of the GDISC1 pin (level or edge mode),
as follows:
1 =Edge
0 = Level (default)
6.15.6
VPX GDISC1 Active Low/High Register (0x68D)
Bit 7 sets the interrupt detection sensitivity of the GDISC1 pin (active high/low or
rising/falling edge depending on whether the pin is in level or edge mode), as
follows:
1 =Active high/rising edge
0 =Active low/falling edge (default)
