Publication No. SBC329-HRM/1
FPGA Registers 85
6.10 AXIS Registers
6.10.1
AXIS Timestamp Registers (0x648 to 0x64D)
These can be used to read the 48-bit timestamp. Reading register 0 latches the current
timestamp value into registers 1 to 5, so register 0 must always be read first.
AXIS Timestamp Register Address Timestamp Value Bits
Default
0
0x648
7 to 0 (least significant byte)
N/A
1
0x649
15 to 8
N/A
2
0x64A
23 to 16
N/A
3
0x64B
31 to 24
N/A
4
0x64C
39 to 32
N/A
5
0x64D
47 to 40 (most significant byte) N/A
6.10.2
AXIS Clock Frequency Register (0x64E)
This returns the AXIS master clock period in nanoseconds. It returns the value 0xFA,
which equals 250 ns, giving a 4.0 MHz clock.
6.10.3
AXIS Clock Control Register (0x64F)
Bits
Read/Write Description
Default
7
Read/Write
AXIS master enable:
1 = Drive AXIS clock onto GPIO2 and allow GPIO3 to be driven as AXIS reset
(GPIO2 and GPIO3 interrupts are automatically disabled and outputs inhibited)
0 = Do not drive clock onto GPIO2; GPIO2 and GPIO3 behave as GPIO signals
0
6
Read/Write
AXIS reset signal:
1 = Assert AXIS reset signal on GPIO3
0 = De-assert AXIS reset signal on GPIO3
This bit is only functional when bit 7 is set
N/A
5 to 0
Read only
Reserved
000000
b
