XVME-682 Manual
October, 1989
SERCLK1B:21
SERDAT1B:22
SYSCLK1A:10
Table A-1 JI - VMEbus Signal Identification cont.
Signal
Mnemonic
DOO-D15
GND
IACK*
IRQ1*-
IRQ7*
LWORD*
Connector
and
Pin Number
1A:1-8
IC:1-8
IA:9,11,
15,17,19,
I B:20,23,
1C:9
2B:2,12,
22,31
1A:20
1B:24-30
IC:13
(RESERVED) 2B:3
Signal Name and Description
DATA BUS (bits 0-15): Three-state driven, bi-directional data lines
that provide a data path between the DTB master and slave.
GROUND
INTERRUPT ACKNOWLEDGE: Open-collector or three-state
driven signal from any master processing an interrupt request.
It is routed via the backplane to slot 1, where it is looped-back to
become slot I IACKIN* in order to start the interrupt acknowledge
daisy-chain.
INTERRUPT REQUEST (1-7): Open-collector driven signals,
generated by an interrupter, which carry prioritized interrupt
requests. Level seven is the highest priority.
LONGWORD: Three-state driven signal indicates that the current
transfer is a 32-bit transfer.
RESERVED: Signal line reserved for future VMEbus
enhancements. This line must not be used.
A reserved signal which will be used as the clock for a serial
communication bus protocol which is still being finalized.
A reserved signal which will be used as the transmission line for
serial communication bus messages.
SYSTEM CLOCK: A constant 16-MHz clock signal that is
independent of processor speed or timing. It is used for general
system timing use.
A-3
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Summary of Contents for XVME-682
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