XVME-682 Manual
October, 1989
ROM
BIOS
80286
CPU
80287
NPX
MATH COPROCESSOR
BUFFERS
(OPTIONAL)
1.4 MBYTES DUAL-
PORTED RAM
VMEbus
MASTER/SLAVE I/F
Appendix D
BLOCK DIAGRAMS, ASSEMBLY DRAWINGS, & SCHEMATICS
NOTE
These schematics and assembly drawings are for the
Revision Level C artwork ONLY.
XVME-682 CPU BLOCK DIAGRAM
PC/AT BUS I/F
COM 1 COM 2 L P T 1
WATCHDOG
TIMER
KEYBOARD
liF
LOCAL AT BUS
D-1
TWO SERIAL
PORTS
BATTERY-BACKED
TOD CLOCK
PARALLEL
INTERFACE
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Summary of Contents for XVME-682
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