XVME-682 Manual
October, 1989
When the local 80286 processor receives an interrupt on IRQ10 - IRQI2 or IRQ15, the user
program must read the AUX INT port to determine the VMEbus interrupt level. The user p
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the VMEbus IACK cycle. Software should check to ensure the VMEbus interrupter has
negated its interrupt before leaving the ISR (interrupt service routine).
6.5.2 Dual-Port Interrupts
Another VMEbus master may interrupt the XVME-682 by reading any one of the lower 16
bytes of the module's dual port RAM. When this access occurs the dual port interrupt is
latched and remains latched until bit 7 of CONREG is reset. The status of this interrupt is
available in AUX_INT bit 0. When bit 0 is set the interrupt is pending. The dual port
interrupt must be cleared by resetting bit 7 of CONREG.
A jumper is provided to enable\disable this interrupt, when J I is IN the dual port interrupt
is enabled, when OUT the interrupt is disabled. See Figure 6-3 for a diagram of the XVME-
682 Auxiliary Maskable Interrupt Structure.
6.5.3 Auxiliary Non-Maskablc Interrupts
0
Four non-maskable interrupts have been added to the basic IBM PC/AT architecture. These
four auxiliary non maskable interrupts (ANMIs) are: the abort button, the watchdog timer,
SYSFAIL, and ACFAIL. See Figure 6-4.
The IBM PC/AT architecture provides a mechanism to disable and enable NMIs. An output to
port 70h with D7=0 will enable NMIs. An output to port 70h with D7=1 will disable NMIs.
This same mechanism will enable and disable the ANMIs. All four ANMIs are implemented
as latches.
When the interrupt event occurs, and is enabled, the latch will set. The latch remains set until
the interrupt is disabled or a system reset occurs.
SYSFAIL, ACFAIL, and the abort button are all enabled by bit 4 of CONREG. If bit 4 is on,
the occurrence of the interrupt event will set a latch, which remains set until bit 4 is reset.
When the latch is set a NMI will occur if module NMI is enabled.
The state of these latches can be determined by checking input port STATUS_1. SYSFAIL
latch is bit 2, ACFAIL latch is bit 1, and the abort button latch is bit 3. When these bits are
high the corresponding latch is set.
The watchdog timer (WDT) ANMI is enabled by bit 0 of CONREG. The WDT has a timeout
period of approximately 150 ms. If bit 0 of CONREG is set and the WDT expires, a latch will
set and remain set until bit 0 of CONREG is reset. If the module NMI is enabled, the setting
of this latch will generate a module ANMI.
The state of this latch is available in bit 7 as input port STATUS__2. When the latch is set,
bit 7 will read 0, when the latch is reset, the bit will read 1.
6-13
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Summary of Contents for XVME-682
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