Production Data
WM8580
w
PD, Rev 4.7, March 2009
57
f
2
TO PLLxCLK DIVISION FACTOR
POSTSCALE_x
FREQMODE_x[1:0]
0 1
00
÷2 ÷4
01
÷4 ÷8
10
÷8 ÷16
11
÷12 ÷24
Table 50 PLL User Mode Clock Divider Configuration
POSTSCALE_A
PLLACLK FREQUENCY
0
256fs
1
128fs
Table 51 PLL S/PDIF Receiver Mode Clock Divider Configuration
PLL CONFIGURATION EXAMPLE
Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and
the required PLLBCLK frequency is 12.288MHz.
1.
Calculate the f
2
, FREQMODE_B and POSTSCALE_B Values
The PLL is designed to operate with best performance when the f
2
clock is between 90 and 100MHz.
The necessary PLLBCLK frequency is 12.288MHz. Choose POSTSCALE_B and FREQMODE_B
values to set the f
2
frequency in the range of 90 to 100MHz. In this case, the default values
(POSTSCALE_B = 0 and FREQMODE_B[1:0] = 10) will configure the f
2
to PLLBCLK divider as 8
and hence will set the f
2
frequency at 98.304MHz; this value is within the 90 to 100MHz range and is
hence acceptable.
•
POSTSCALE_B
=
0
•
FREQMODE_B [1:0] = 10b
•
f
2
= 98.304MHz
2. Calculate R Value
Using the relationship: R = (f
2
÷ f
1
), the value of R can be calculated.
•
R
=
(f
2
÷ f
1
)
•
R = (98.304 ÷ 12)
•
R
=
8.192
3. Calculate PLLB_N Value
The value of PLLB_N is the integer (whole number) value of R, ignoring all digits to the right of the
decimal point. In this case, R is 8.192, hence PLLB_N is 8.
4. Calculate PLL_K Value
The PLLB_K value is simply the integer value of (2
22
(R-PLLB_N)).
•
PLLB_K = integer part of (2
22
x (8.192 – 8))
•
PLLB_K = integer part of 805306.368
•
PLLB_K = 805306 (decimal) / C49BA (hex)
A number of example configurations are shown in Table 52. Many other configurations are possible;
Table 52 shows only a small number of valid possibilities. As both PLLs are identical, the same
configuration procedure applies for both.
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