WM8580
Production
Data
w
PD, Rev 4.7, March 2009
10
Test Conditions
AVDD, PVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, PGND, DGND = 0V, T
A
= +25
o
C, 1kHz Signal, fs = 48kHz, 24-
Bit Data, Slave Mode, MCLK, ADCMCLK = 256fs, 1V
rms
Input Signal Level unless otherwise stated.
PARAMETER SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
1kHz 100mV
p-p
50 dB
Power Supply Rejection Ratio
(See note 4)
PSRR
20Hz to 20kHz
100mV
p-p
45 dB
ADC Performance WM8580AGEFT/V, WM8580AGEFT/RV (+25
˚
C)
Full Scale Input Signal Level (for
ADC 0dB Input)
1.0
x
VREFP/5
V
rms
Input resistance
6
k
Ω
Input capacitance
10
pF
A-weighted,
@ fs = 48kHz
90 100 dB
Unweighted,
@ fs = 48kHz
97 dB
A-weighted,
@ fs = 48kHz, AVDD =
3.3V
97 dB
A-weighted,
@ fs = 96kHz
97 dB
Unweighted,
@ fs = 96kHz
94 dB
A-weighted,
@ fs = 96kHz, AVDD =
3.3V
94 dB
A-weighted,
@ fs = 192kHz
97 dB
Unweighted,
@ fs = 192kHz
94 dB
Signal to Noise Ratio (See
Terminology 1,2,4)
SNR
A-weighted,
@ fs = 192kHz, AVDD
= 3.3V
94 dB
1kHz, -1dB Full Scale
@ fs = 48kHz
-87
-80
dB
1kHz, -1dB Full Scale
@ fs = 96kHz
-86 dB
Total Harmonic Distortion
THD
1kHz, -1dB Full Scale
@ fs = 192kHz
-85 dB
Dynamic Range
DNR
-60dB FS
90
100
ADC Channel Separation
1kHz Input
97
dB
Channel Level Matching (See
Terminology 4)
1KHz
Signal 0.1 dB
Channel Phase Deviation
1kHz
Signal
0.0001
Degree
Offset Error
HPF
On
HPF Off
0
100
LSB
LSB
Digital Logic Levels (CMOS Levels)
Input LOW level
V
IL
0.3
x
DVDD
V
Input HIGH level
V
IH
0.7 x DVDD
V
Input leakage current
-1
±0.2
+1
µA
Input capacitance
5
pF
Output LOW
V
OL
I
OL
=1mA
0.1
x
DVDD
V
Output HIGH
V
OH
I
OH
=
-1mA
0.9 x DVDD
V
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