Production Data
WM8580
w
PD, Rev 4.7, March 2009
79
MUTE
DESCRIPTION
0
Normal Operation
1
Mute DAC channels
Floating
MUTE is an output to indicate when Zero Detection occurs on all DACs
(ZFLAG).
H = detected, L = not detected.
Table 80 MUTE Pin Control Options
PRIMARY AUDIO INTERFACE (TX) MASTER MODE CONTROL
In Hardware Control Mode, the SDIN pin is used to enable the master mode function on the Primary
Audio Interface transmitter. This has the same operation as the PAIFTX_MS register bit. The
PAIFTX_RATE default settings of 256fs, and 64 BCLKs/LRCLK for BCLKSEL, are used in Hardware
Control Mode. See section headed “DIGITAL AUDIO INTERFACES” for more information on master
mode operation.
SDIN AUDIO
INTERFACE
(TX)
0 Slave
1 Master
Table 81 Audio Interface (Transmitter) Master Mode Hardware Mode Control
S/PDIF ERROR HANDLING
Should the incoming S/PDIF sub-frame contain a parity error or a bi-phase encoding error, it is
assumed the sub-frame has become corrupted. Similarly, if VALIDITY is detected as 1, it is assumed
the data within the S/PDIF frame is invalid. Under these conditions, the S/PDIF Receiver repeats the
last valid sample in place of the corrupted/invalid samples. (Note: For the S/PDIF receiver to S/PDIF
transmitter path, only VALIDITY errors will cause data to be overwritten – parity and bi-phase errors
have will not cause data to be overwritten).
POWERDOWN CONTROL
In Software Control Mode, the chip is powered-down by default. In Hardware Control Mode, the chip
is powered-up by default but can be powered down by setting the ALLPD(MFP7) input high. (Note
that in Software Control Mode, this pin takes the function of SAIF_LRCLK or GPO7).
ALLPD (MFP7)
0 1
Powerup Powerdown
Table 82 Hardware Mode Powerdown Control
HARDWARE CONTROL CLOCK ROUTING
In hardware mode the user has no access to the internal clock routing . In this mode the automatic
clock routing provides maximum functionality. In harware mode the OSCCLK must be 12MHz. no
other OSCCLK frequencies are supported.
MASTER MODE
If the S/PDIF Rx interface is enabled, then an internal MCLK is generated at 256fs. This internal
clock will act as a source clock for ADC, DACs and PAIF. The PAIF will output the PAIFTX_BCLK
and the PAIF_LRCLK. The MCLK is not available as an output (MCLK pin defaults to an input). The
SAIF is not available in hardware mode.
If the S/PDIF is disabled and the ADC is used as the source for the DACs or PAIF, then an MCLK
clock must be provided via the ADCMCLK input pin.
If the PAIF sources the ADC and the DACs source the S/PDIF, then the PAIF will operate from an
MCLK generated from the ADCMCLK input clock and the DACs will operate from an internal MCLK
(256fs) generated from S/PDIF interface.
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