Production Data
WM8580
w
PD, Rev 4.7, March 2009
85
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
2:0
SAIF_RATE
[2:0]
010
Master Mode LRCLK Rate
000 = 128fs
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
4:3
SAIF_BCLKSEL
[1:0]
00
Master Mode BCLK Rate
00 = 64 BCLKs per LRCLK
01 = 32 BCLKs per LRCLK
10 = 16 BCLKs per LRCLK
11 = BCLK = System Clock
5
SAIFMS
0
SAIF Master/Slave Mode Select
0 = Slave Mode
1 = Master Mode
R11
SAIF1
0Bh
7:6 SAIFMS_
CLKSEL
[1:0]
11
SAIF Master Mode clock source
00 = ADCMCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
1:0 PAIFRXFMT
[1:0]
10
PAIF Receiver Audio Data Format Select
11: DSP Format
10: I
2
S Format
01: Left justified
00: Right justified
3:2 PAIFRXWL
[1:0]
10
PAIF Receiver Audio Data Word Length
11: 32 bits (see Note)
10: 24 bits
01: 20 bits
00: 16 bits
4 PAIFRXLRP
0
In LJ/RJ/I
2
S modes
0 = LRCLK not inverted
1 = LRCLK inverted
In DSP Format:
0 = DSP Mode A
1 = DSP Mode B
5
PAIFRXBCP
0
PAIF Receiver BCLK polarity
0 = BCLK not inverted
1 = BCLK inverted
6 DACOSR
0 DAC Oversampling Rate Control
0= 128x oversampling
1= 64x oversampling
R12
PAIF 3
0Ch
8:7 DAC_SRC
[1:0]
11 DAC1
Source:
00 = S/PDIF received data.
10 = SAIF Receiver data
11 = PAIF Receiver data
Note:
When DAC_SRC = 00, DAC2/3 may be turned off,
depending on RX2DAC_MODE
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