Production Data
WM8580
w
PD, Rev 4.7, March 2009
49
PRIMARY AUDIO INTERFACE TRANSMITTER (PAIF TX)
The PAIF transmitter requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be
supplied externally (slave mode) or they can be generated internally by the WM8580 (master mode).
Register R10, bit 5 selects master or slave mode.
In Slave mode, the BCLK driving the PAIF Tx interface is either the PAIFTX_BCLK pin (default) or
the PAIFRX_BCLK pin (if ADC is using MCLK pin). The LRCLK driving the PAIF Tx interface is the
PAIFRX_LRCLK
In master mode the BCLK and LRCLK driving the PAIF Tx interface are generated by the Master
Mode Clock Gen module. The control of this module is described on page 22.
The clock supplied to the Master Mode Clock Gen module can be ADCMCLK, PLLACLK, PLLBCLK,
or MCLK. Selection is automatic and is based on the digital routing configuration. Figure 30 illustrates
the clock configuration and Table 41 gives some examples of clock routing based on digital routing
configuration.
Figure 30 PAIF Tx Interface Clock Configuration
Digital Routing
Configuration
Clock used by PAIF Tx
Master Mode Clock
Generator
Comments
PAIF Tx = S/PDIF RX
PLLACLK
Recommend to operate PAIF Tx in master
mode
PAIF Tx = SAIF RX
Same as ADC_CLK
PAIF Tx selects the same as ADC_CLK_I
Table 41 PAIF Tx Clock Configuration Examples
Secondary Audio Interfaces (SAIF Rx & SAIF TX)
The SAIF Transmit and Receive interfaces share a common LRCLK and a common BCLK. These
can be supplied externally (slave mode) or they can be generated internally by the WM8580 (master
mode). Register R11, bit 5 selects master or slave mode.
In Slave mode, the BCLK driving the SAIF interface is the SAIF_BCLK pin and the LRCLK driving the
SAIF interface is the SAIF_LRCLK pin
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