LISA-U2 series - System integration manual
UBX-13001118 - R27
Design-In
Page 142 of 183
C1-Public
2.5.3.2
RESET_N pin
The following precautions are suggested for the
RESET_N
line of LISA-U2 modules, depending on the
application board handling, to satisfy the ESD immunity test requirements:
•
A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) must be mounted on the line
termination connected to the
RESET_N
pin to avoid a module reset caused by an electrostatic
discharge applied to the application board enclosure
•
A proper series chip ferrite bead noise/EMI suppression filter (e.g. Murata BLM15HD182SN1)
must be added on the line connected to the
RESET_N
pin to avoid a module reset caused by an
electrostatic discharge applied to the application board enclosure
•
A 220 nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be mounted as close as
possible to the
RESET_N
pin of LISA-U2 series modules to avoid a module reset caused by an
electrostatic discharge applied to the application board enclosure
•
It is recommended to keep the connection line to
RESET_N
as short as possible
The maximum ESD sensitivity rating of the
RESET_N
pin is 1 kV (Human Body Model according to
JESD22-A114F). Higher protection levels could be required if the
RESET_N
pin is externally accessible
on the application board. The following precautions are suggested to achieve higher protection levels:
•
A general purpose ESD protection device (e.g. EPCOS CA05P4S14THSG varistor array or EPCOS
CT0402S14AHSG varistor) should be mounted on the
RESET_N
line, close to the accessible point
The
RESET_N
application circuit implemented in the EMC / ESD approved reference designs of the
LISA-U2 series modules is described in
(section
2.5.3.3
SIM interface
The following precautions are suggested for the LISA-U2
module’s SIM interface (
VSIM
,
SIM_RST
,
SIM_IO
,
SIM_CLK
pins), depending on the application board handling, to satisfy the ESD immunity
test requirements:
•
A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) must be mounted on the lines
connected to
VSIM
,
SIM_RST
,
SIM_IO
and
SIM_CLK
pins to assure SIM interface functionality
when an electrostatic discharge is applied to the application board enclosure
•
It is suggested to use as short as possible connection lines at the SIM pins
The maximum ESD sensitivity rating of SIM interface pins is 1 kV (Human Body Model according to
JESD22-A114F). Higher protection levels could be required if SIM interface pins are externally
accessible on the application board. The following precautions are suggested to achieve higher
protection levels:
•
A low capacitance (i.e. less than 10 pF) ESD protection device (e.g. Infineon ESD8V0L2B-03L or
AVX USB0002) should be mounted on each SIM interface line, close to the accessible points (i.e.
close to the SIM card holder)
The SIM interface application circuit implemented in the EMC / ESD approved reference designs of
LISA-U2 series modules versions is described in section
2.5.3.4
Other pins and interfaces
All the module pins that are externally accessible on the device integrating the LISA-U2 module should
be included in the ESD immunity test since they are considered to be a port as defined in ETSI EN 301
489-1
. Depending on applicability, to satisfy the ESD immunity test requirements according to
