Ublox LISA-U2 Series, System Integration Manual

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LISA-U2 series - System integration manual
UBX-13001118 - R27 Design-In Page 117 of 183
C1-Public
2 Design-In
2.1 Design-in checklist
This section provides a design-in checklist.
2.1.1 Schematic checklist
The following are the most important points for a simple schematic check:

DC supply must provide a nominal voltage at the VCC pin above the minimum operating range
limit.

DC supply must be capable of providing 2.5 A current pulses, providing a voltage at the VCC pin
above the minimum operating range limit and with a maximum 400 mV voltage drop from the
nominal value.

VCC supply should be clean, with very low ripple/noise: provide the suggested series ferrite bead
and bypass capacitors, in particular if the application device integrates an internal antenna.

VCC voltage must ramp from 2.5 V to 3.2 V within 1 ms to allow a proper switch-on of the
module.

Do not leave PWR_ON floating: add a pull-up resistor to V_BCKP .

Do not apply loads which might exceed the limit for maximum available current from the V_INT
supply.

Check that the voltage level of any connected pin does not exceed the specific operating range.

Capacitance and series resistance must be limited on each SIM signal to match the SIM
specifications.

Insert the suggested low capacitance ESD protection and passive filtering parts on each SIM
signal.

Check the UART signal directions, since the signal names follow the ITU-T V.24
Recommendation
[3] .

Provide appropriate access to the USB interface and/or to the UART RxD , TxD lines and access
to the PWR_ON and/or RESET_N lines to flash/upgrade the module firmware using the u-blox
EasyFlash tool.

Provide appropriate access to the USB interface and/or to the UART RxD , TxD , CTS , RTS lines
for debugging purposes.

Capacitance and series resistance must be limited on each line of the SPI / IPC interface.

Add a suitable pull-up resistor to an appropriate supply on each DDC (I2C) interface line, if the
interface is used.

Capacitance and series resistance must be limited on each line of the DDC interface.

Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kΩ
resistor on the board in series to the GPIO when those are used to drive LEDs.

Connect pin number 5 ( RSVD ) to ground.

Check the digital audio interface specifications to connect a relevant device.

Capacitance and series resistance must be limited on the CODEC_CLK line and each I2S
interface line.

Provide suitable precautions for ESD immunity as required on the application board.

Any external signal connected to the UART interface, SPI/IPC interface, I2S interfaces and
GPIOs must be tri-stated when the module is in power-down mode, when the external reset is