Ublox LISA-U2 Series, System Integration Manual

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LISA-U2 series - System integration manual
UBX-13001118 - R27 System description Page 12 of 183
C1-Public
Function Pin Module No I/O Description Remarks
SPI SPI_MISO All 57 O
SPI Data Line
Output
Module Output: module runs as SPI local device.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
Idle high.
See section
1.9.4
SPI_MOSI All 56 I SPI Data Line
Input
Module Input: module runs as SPI local device.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
Idle high.
Internal active pull-up to
V_INT (1.8 V) enabled.
See section 1.9.4
SPI_SCLK All 55 I SPI Serial Clock
Input
Module Input: module runs as SPI local device.
Idle low (CPOL=0).
Internal active pull-down to
GND enabled.
See section 1.9.4
SPI_SRDY All 58 O SPI local device
ready output
Module Output: module runs as SPI local device.
Idle low.
See section
1.9.4
SPI_MRDY All 59 I
SPI host ready
input
Module Input: module runs as SPI local device.
Idle low.
Internal active pull- down to
GND enabled.
See section 1.9.4
DDC SCL All 45 O I2C bus clock line Fixed open drain. External pull-up required.
See section 1.10
SDA All 46 I/O I2C bus data line
Fixed open drain. External pull-up required.
See section 1.10
UART RxD All 16 O UART data output Circuit 104 (RxD) in ITU-T V.24.
Provide access to the pin for FW update and
debugging if the USB interface is connected
to the application processor.
See section
1.9.2
TxD All 15 I UART data input Circuit 103 (TxD) in ITU-T V.24.
Internal active pull-up to V_INT (1.8 V) enabled.
Provide access to the pin for FW update and
debugging if the USB interface is connected
to the application processor.
See section
1.9.2
CTS All 14 O UART clear to
send output
Circuit 106 (CTS) in ITU-T V.24.
Provide access to the pin for debugging if the
USB interface is connected to the application
processor.
See section
1.9.2
RTS All 13 I UART ready to
send input
Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to
V_INT (1.8 V) enabled.
Provide access to the pin for debugging if the
USB interface is connected to the application
processor.
See section
1.9.2
DSR All 9 O UART data set
ready output
Circuit 107 (DSR) in ITU-T V.24.
See section
1.9.2
RI All 10 O UART ring
indicator output
Circuit 125 (RI) in ITU-T V.24.
See section
1.9.2
DTR All 12 I UART data
terminal ready
input
Circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up to
V_INT (1.8 V) enabled.
See section 1.9.2
DCD All 11 O UART data carrier
detect output Circuit 109 (DCD) in ITU-T V.24.
See section
1.9.2