Ublox LISA-U2 Series, System Integration Manual

Page: 44 / 183

LISA-U2 series - System integration manual
UBX-13001118 - R27 System description Page 44 of 183
C1-Public
Following are some typical examples of application circuits using the RESET_N input pin.
The simplest way to reset the module is to use a push button that shorts the RESET_N pin to ground.
If RESET_N is connected to an external device (e.g. an application processor on an application board),
an open drain output can be directly connected without any external pull-up. A push-pull output can
be used too: in this case, make sure that the high level voltage of the push-pull circuit is below the
maximum voltage operating range of the
RESET_N pin (specified in the RESET_N pin characteristics
table in the LISA-U2 series data sheet [1] ). To avoid unwanted resets of the module, make sure to fix
the proper level at the RESET_N input pin in all possible scenarios.
As ESD immunity test precaution, a 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01), a
proper series chip ferrite bead noise/EMI suppression filter (e.g. Murata BLM15HD182SN1) and a 220
nF bypass capacitor (e.g. Murata GRM155R60J224KE01) must be added as close as possible to the
RESET_N pin of LISA-U2 series modules to avoid a module reset caused by an electrostatic discharge
applied to the application board (for more details, see section 2.5.3 ).
LISA-U2 series
2
V_BCKP
22
RESET_N
Reset
push button
ESD
Open
Drain
Output
Application
processor
LISA-U2 series
2
V_BCKP
22
RESET_N
Rint
Rint
EMI1
C1
EMI2
C3
C2
C4
Figure 20: RESET_N application circuits using a push button and an open drain output of an application processor
Reference Description Remarks
ESD Varistor for ESD protection. CT0402S14AHSG - EPCOS
C1, C3 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata
C2, C4 220 nF Capacitor Ceramic X5R 0402 10% 6.3 V GRM155R60J224KE01 - Murata
EMI1, EMI2 Chip Ferrite Bead Noise/EMI Suppression
Filter 1800
Ω
at 100 MHz, 2700
Ω
at 1 GHz
BLM15HD182SN1 - Murata
Rint 10 k
Ω
Resistor 0402 5% 0.1 W Internal pull-up resistor
Table 19: Example of ESD protection components for the RESET_N application circuit
☞
Any external signal connected to the UART, SPI/IPC, I2S and GPIOs must be tri-stated when the
module is in power-down mode, when the external reset is forced low and during the module power-
on sequence (at least for 3 seconds after the start-up event), to avoid latch-up of circuits and allow
a clean boot of the module. If the external signals connected to the cellular module cannot be tri-
stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244,
TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance
during module power-down mode, when external reset is forced low and during the power-on
sequence.