Toshiba SD-2300, Service Manual

Page: 117 / 160

Table 3-5-4 TMP93CS44 (3/3)
Pin
No.
74
72
73
4
22
23
25
32
20
24
21
30
57
13
31
28
29
Function
A/D converter GND terminal (0V).
Reference voltage input terminal (H) for A/
D converter
Reference voltage input terminal (L) for A/
D converter
Nonmaskable interrupt request terminal:
Interrupt request terminal with the signal at
rising/falling edge programmable.
High frequency oscillation connection
terminal.
High frequency oscillation connection
terminal.
Reset: Initializes TMP93CS44/S45 (Pull-up
resistance is built in.)
Address latch enable (Available to set
output enable to reduce noise).
Clock output: develops clock signal divided
in fsys two. It is pulled up during the reset.
(Available to set output enable to reduce
noise)
External access.
Connect to VCC in TMP93CS44.
Address mode: Selection terminal of the
external data bus width.
(TMP93CS44)
Connect the terminal to VCC. Data bus
width at accessing to external can be set
by the wait control resistor, port 1 control
resistor.
Power supply terminal (connect all VCC
terminals to the power supply).
GND terminal (connect all VSS terminals to
GND (0V)).
Terminal for test. (Connect the both
terminals on the PC board.
Name
AVSS
VREFH
VREFL
NIMI
X1
X2
RESET
ALE
CLK
EA
AM8/16
VCC
VSS
TEST1,
TEST2
Note: The terminals with pull-up resistors other than RESET
terminal can be separated the resistors from the terminals
electrically by using the software.
Table 3-5-5 XCMMPL3CZP (1/2)
Group
SDRAM
port
ROM port
System
Bus
(Internal
Mode)
System
Bus
(External
Mode)
Function
DRAM data bus
DRAM MUX address
Main memory address bus bit 13/
Data byte mask for bank 2
Main memory address bus bit 12/
Data byte mask for bank 2
Column strobe
Row Strobe
Chip selects
Byte selects
Read/Write enable
SDRAM clock input
SDRAM clock output
Multiplexed address/data
ROM address latch enables
ROM chip select
White enable (for SRAM/FLASH)
Output Enable
System bus data
System bus address
System bus address
Chip select
Bus Request
Bus Grant
Bus Busy
Bus Clock output - CLKIN/2
Data ready signal
System bus data
System bus address
System bus address
System bus address bit 1
System bus address bit 0
System Memory Address Mux
Control
Chip select
Bus Request
Bus Grant
Bus Busy
Transfer acknowledge
Burst Transfer
Bus Clock output - CLKIN/2
Data ready signal
Transfer start
Name
SD_DQ (15:0)
SD_A (11:0)
SD_A (13)/
SD_DQMB2 [1]
SD_A (12)/
SD_DQMB2 [0]
SD_CAS_B
SD_RAS_dB
SD_CS_B (1:0)
SD_DQM (1:0)
SD_WE_B
SD_CLK_IN
SD_CLK
ROM_D (7:0)
ROM_LAT (2:0)
ROM_CS_B
ROM_WE_B
ROM_OE_B
SYSD (31:0)
SYSA (22:2)
SYSA [24:23]/
SYSA [1:0]
SYSCS
SYSBR
SYSBG
SYSBB
SYSBCLK
SYSRDY_B
SYSD (31:0)
SYSA (22:2)
SYSA [24:23]
SYSA [1]
SYSA [0]
SYSAMUX
SYSCS
SYSBR
SYSBG
SYSBB
SYSTA
SYSBURST
SYSBCLK
SYS_RDY_B
SYSTS [1:0]