Toshiba Portege R400 Series, Maintenance Manual, Page: 61 / 369

2 Troubleshooting Procedures
PORTEGE R400 Maintenance Manual (960-623) [CONFIDENTIAL] 2-23
Table 2-4 Debug port (Boot mode) error status (3/10)
D port status Inspection items Details
Micro code Update(
HTT Support model)
Prohibition of cache
F100H
L1/L2 Cache of Flash ROM area are
permitted.
Initialization of MCHM
I nitialization of ICH7M.D30.Func0
Initialization of ICH7M.D31.Func1
Initialization of ICH7M.D31.Func1/2
Initialization of
I USB Controller
Initialization of ICH7M.D31.Func3
Initialization of H/W (before DRAM
recognition)
Initialization of TI Controller
Initialization of PIT channel 1
(Setting the refresh interval to “30
μ
s”)
Check of DRAM type and size
(at cold boot)
When unsupported memory is connected,
becoming HLT after beep sound (HLT when
DRAM size is 0) F101H
SM-RAM stack area test HLT When it can not be used as a stack
Cache configuration
Cache permission (L1/L2 Cache)
CMOS access test (at cold boot) (HLT when an error is detected)
Battery level check of CMOS
CMOS checksum check
Initialization of CMOS data (1)
Setting of IRT status
(Setting of boot status and IRT busy flag, The rest
bits are 0)
F102H
Storing DRAM size in CMOS
F103H
Resume branch (at cold boot) Not resume when a CMOS error occurred
Not resume when resume status code is not set
Resume error check
S3 returning error (ICH)
Resume error F17A RSM_UNKNOWN_ERR
SM-RAM checksum check
Resume error F173H RSM_SMRAM_ERR