Cinterion
®
MV31-W Hardware Interface Description
3.2 Characteristics
75
t
MV31-W_HID_v01.009a
2022-04-27
Public / Preliminary
Page 32 of 76
3.2.7
PCI Express
®
Interface
The PCI Express
®
Interface with a 1
st
and 2
nd
lane is compliant to
. Please note that with the
data card’s USB 3.1 hardware variant the PCIe’s 2
nd
lane pins are used as USB 3.1 interface
pins.
PCIe
®
Design General Guidelines:
•
All sensitive/high high-speed signals and circuits must be protected from PCIe
®
corruption,
e.g. noisy signal, crosstalk and RF.
•
Pay extra attention to crosstalk, ISI, and intra-lane skew and impedance discontinuities.
•
Each trace needs to be adjacent to a ground plane.
•
PCIe
®
PERx0/1, PETx0/1, REFCLK: 90 Ohm differential, +/ -10% trace impedance.
•
AC coupling capacitor should be added in an application board: 220nF
- Place 220nF capacitors on PCIe
®
PETx0/1 paths at module side
(already included in MV31-W)
- Place 220nF capacitors on PCIe
®
PETx0/1 paths at platform side.
•
Reserve choke on all the PCIe
®
signals in platform for noise reduction
•
Tx differential pair length matching < 0.5mm.
•
Rx differential pair length matching < 0.5mm.
Figure 13:
PCIe
®
Interface
3.2.7.1
PERST# Signal
The PERST# signal resets the PCIe Interface of the 5G M.2 Data Card MV31-W. After releas-
ing the PERST# line, i.e., with a change of the signal level from low to high, the interface re-
starts.
It is recommended to control this PERST# line with an open collector transistor or an open drain
field-effect transistor.
