Thales Cinterion MV31-W, Hardware Interface Description

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Cinterion ® MV31-W Hardware Interface Description
3.2 Characteristics
75
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MV31-W_HID_v01.009a 2022-04-27
Public / Preliminary
Page 31 of 76
3.2.6 USB Interface
The 5G M.2 Data Card MV31-W has 6 interface lines for USB (see Figure 12 ) and is acting as
peripheral.
USB Design General Guidelines:
•
Reserve choke on all the USB signals in platform for noise debug.
• Reserve 0.1uF capacitor on USB3.1 TX/Rx paths.
• Co-layout USB3 choke and 0.1uF capacitor on module side for noise debug
Notes: All the above components should be covered by shielding cover.
Figure 12: USB Interface
3.2.6.1 USB 2.0 Interface
The 5G M.2 Data Card MV31-W‘s USB interface (USB_D+, USB_D-) as part of the 75-pin ap-
plication connector supports a USB 2.0 High Speed (480Mbit/s) device interface that is Full
Speed (12Mbit/s) compliant. Because there is no separate voltage detection line available on
the application connector, the 5G M.2 Data Card MV31-W reports as a self-powered device
compliant with the
[5] .
3.2.6.2 USB 3.1 Gen 2 Interface
The USB 3.1 Gen 2 Interface is compliant to [6] and supports up to 10Gbit/s.
Please note that with the data card’s PCIe hardware variant the USB 3.1 interface pins are
used as PCIe 2
nd
lane pins.
USB_D ‐
USB_D+
USB3.1 ‐ TX ‐
USB3.1 ‐ TX+
USB3.1 ‐ RX ‐
USB3.1 ‐ RX+
USB_D ‐
USB_D+
USB3.1 ‐ RX ‐
USB3.1 ‐ RX+
USB3.1 ‐ TX ‐
USB3.1 ‐ TX+
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