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SLOS787H – MAY 2012 – REVISED APRIL 2014

4.2

Terminal Functions

describes the signals.

Table 4-1. Terminal Functions

TERMINAL

TYPE

(1)

DESCRIPTION

NAME

NO.

V

DD_A

1

OUT

Internal regulated supply (2.7 V to 3.4 V) for analog circuitry

V

IN

2

SUP

External supply input to chip (2.7 V to 5.5 V)

V

DD_RF

3

OUT

Internal regulated supply (2.7 V to 5 V), normally connected to V

DD_PA

(pin 4)

V

DD_PA

4

INP

Supply for PA; normally connected externally to V

DD_RF

(pin 3)

TX_OUT

5

OUT

RF output (selectable output power, 100 mW or 200 mW, with V

DD

= 5 V)

V

SS_PA

6

SUP

Negative supply for PA; normally connected to circuit ground

V

SS_RX

7

SUP

Negative supply for RX inputs; normally connected to circuit ground

RX_IN1

8

INP

Main RX input

RX_IN2

9

INP

Auxiliary RX input

V

SS

10

SUP

Chip substrate ground

BAND_GAP

11

OUT

Bandgap voltage (V

BG

= 1.6 V); internal analog voltage reference

Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for Direct Mode 0 or 1.

ASK/OOK

12

BID

Can be configured as an output to provide the received analog signal output.

IRQ

13

OUT

Interrupt request

INP

External data modulation input for Direct Mode 0 or 1

MOD

14

OUT

Subcarrier digital data output (see registers 0x1A and 0x1B)

V

SS_A

15

SUP

Negative supply for internal analog circuits; connected to GND

V

DD_I/O

16

INP

Supply for I/O communications (1.8 V to V

IN

) level shifter. V

IN

should be never exceeded.

I/O_0

17

BID

I/O pin for parallel communication

I/O_1

18

BID

I/O pin for parallel communication

I/O pin for parallel communication

I/O_2

19

BID

TX Enable (in Special Direct Mode)

I/O pin for parallel communication

I/O_3

20

BID

TX Data (in Special Direct Mode)

I/O pin for parallel communication

I/O_4

21

BID

Slave Select signal in SPI mode

I/O pin for parallel communication

I/O_5

22

BID

Data clock output in Direct Mode 1 and Special Direct Mode

I/O pin for parallel communication

I/O_6

23

BID

MISO for serial communication (SPI)

Serial bit data output in Direct Mode 1 or subcarrier signal in Direct Mode 0

I/O pin for parallel communication.

I/O_7

24

BID

MOSI for serial communication (SPI)

Selection of power down mode. If EN2 is connected to V

IN

, then V

DD_X

is active during power

EN2

25

INP

down mode 2 (for example, to supply the MCU).

DATA_CLK

26

INP

Data Clock input for MCU communication (parallel and serial)

If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal
that is used, options are as follows (see register 0x09):

SYS_CLK

27

OUT

13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz

27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz

If EN = 0 and EN2 = 1, then system clock is set to 60 kHz

EN

28

INP

Chip enable input (If EN = 0, then chip is in sleep or power-down mode).

V

SS_D

29

SUP

Negative supply for internal digital circuits

(1)

SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output

Copyright © 2012–2014, Texas Instruments Incorporated

Terminal Configuration and Functions

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Summary of Contents for TRF7964A

Page 1: ... from 13 56 MHz or 27 12 MHz 32 Pin QFN Package 5 mm x 5 mm Crystal or Oscillator 1 2 Applications Public Transport or Event Ticketing Medical Equipment or Consumables Passport or Payment POS Reader Systems Access Control Digital Door Locks Product Identification or Authentication 1 3 Description The TRF7964A device is an integrated analog front end and data framing device for a 13 56 MHz RFID sys...

Page 2: ...C PARITY TRANSMITTER ANALOG FRONT END TX_OUT VDD_PA VSS_PA DIGITAL CONTROL STATE MACHINE CRYSTAL OR OSCILLATOR TIMING SYSTEM EN EN2 ASK OOK MOD OSC_IN OSC_OUT VOLTAGE SUPPLY REGULATOR SYSTEMS SUPPLY REGULATORS AND REFERENCE VOLTAGES VSS_A VSS_RF VDD_RF VDD_X VSS_D VSS VIN VDD_A BAND_GAP RF LEVEL DETECTOR TRF7964A SLOS787H MAY 2012 REVISED APRIL 2014 www ti com 1 4 Functional Block Diagram Figure 1...

Page 3: ...ng Parallel Microcontroller Interface 68 5 1 Absolute Maximum Ratings 9 7 2 TRF7964A Reader System Using SPI With SS 5 2 Recommended Operating Conditions 9 Mode 69 5 3 Electrical Characteristics 10 7 3 Layout Considerations 70 5 4 Handling Ratings 11 7 4 Impedance Matching TX_Out Pin 5 to 50 Ω 70 5 5 Thermal Characteristics 11 7 5 Reader Antenna Design Guidelines 72 5 6 Switching Characteristics 1...

Page 4: ...Device Overview to Section 6 1 12 Changed from By default the AGC is frozen after to By default the AGC window comparator is set after 19 Changed from TX Pulse Length Control register 0x05 to TX Pulse Length Control register 0x06 25 Changed from 18 8 s to 18 8 µs in the sentence that starts with If the register contains all zeros 25 Changed command 0x18 to Test internal RF 46 Changed command 0x19 ...

Page 5: ...n for the TRF7964A device Table 3 1 Supported Protocols Supported Protocols ISO 14443A B FeliCa ISO 15693 Device ISO 18000 3 212 kbps 106 kbps 212 kbps 424 kbps 848 kbps Mode 1 424 kbps TRF7964A Copyright 2012 2014 Texas Instruments Incorporated Device Characteristics 5 Submit Documentation Feedback Product Folder Links TRF7964A ...

Page 6: ...30 29 28 27 26 25 I 0_6 I 0_5 I 0_4 I 0_3 I 0_2 I 0_1 I 0_0 TRF7964A SLOS787H MAY 2012 REVISED APRIL 2014 www ti com 4 Terminal Configuration and Functions 4 1 Pin Assignments Figure 4 1 shows the pin assignments for the 32 pin RHB package Figure 4 1 32 Pin RHB Package Top View 6 Terminal Configuration and Functions Copyright 2012 2014 Texas Instruments Incorporated Submit Documentation Feedback P...

Page 7: ...eded I O_0 17 BID I O pin for parallel communication I O_1 18 BID I O pin for parallel communication I O pin for parallel communication I O_2 19 BID TX Enable in Special Direct Mode I O pin for parallel communication I O_3 20 BID TX Data in Special Direct Mode I O pin for parallel communication I O_4 21 BID Slave Select signal in SPI mode I O pin for parallel communication I O_5 22 BID Data clock ...

Page 8: ... INP Crystal or oscillator input OSC_IN 31 OUT Crystal oscillator output Internally regulated supply 2 7 V to 3 4 V for digital circuit and external devices for example VDD_X 32 OUT MCU Thermal Pad PAD SUP Chip substrate ground 8 Terminal Configuration and Functions Copyright 2012 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links TRF7964A ...

Page 9: ...ended periods may affect device reliability 2 All voltage values are with respect to substrate ground terminal VSS 3 The maximum junction temperature for continuous operation is limited by package constraints Operation above this temperature may result in reduced reliability or lifetime of the device 5 2 Recommended Operating Conditions over operating free air temperature range unless otherwise no...

Page 10: ...utput voltage pin 32 VIN 5 V 3 1 3 4 3 8 V IVDD_Xmax Maximum output current of VDD_X Output current pin 32 VIN 5 V 20 mA Half power mode VIN 2 7 V to 5 5 V 8 12 RRFOUT Antenna driver output resistance 1 Ω Full power mode VIN 2 7 V to 5 5 V 4 6 RRFIN RX_IN1 and RX_IN2 input resistance 4 10 20 kΩ Maximum RF input voltage at RX_IN1 and VRF_INmax VRF_INmax should not exceed VIN 3 5 Vpp RX_IN2 fSUBCARR...

Page 11: ...ng Characteristics TYP operating conditions are TA 25 C VIN 5 V full power mode unless otherwise noted MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DATA_CLK time high or low one half of tLO HI Depends on capacitive load on the I O lines 1 250 62 5 50 ns DATA_CLK at...

Page 12: ...er a broad range of input subcarrier signal options The received signal strength from transponders ambient sources or internal levels is available through the RSSI register The receiver output is selectable among a digitized subcarrier signal and any of the integrated subcarrier decoders The selected subcarrier decoder delivers the data bit stream and the data clock as outputs The TRF7964A also in...

Page 13: ...on for the complete reader system The built in programmable auxiliary voltage regulator VDD_X pin 32 is able to deliver up to 20 mA to supply a microcontroller and additional external circuits within the reader system 6 2 System Block Diagram Figure 6 2 shows a block diagram of the TRF7964A Figure 6 2 System Block Diagram 6 3 Power Supplies The TRF7964A positive supply input VIN pin 2 sources thre...

Page 14: ...DD_X The digital supply regulator VDD_X pin 32 provides the power for the internal digital building blocks and can also be used to supply external electronics within the reader system When configured for 3 V operation the output voltage can be set from 2 7 to 3 4 V in 100 mV steps External bypass capacitors for supply noise filtering must be used per reference schematics Note the configuration of ...

Page 15: ...nd DATA_CLK pins of the reader In typical applications VDD_I O is directly connected to VDD_X while VDD_X also supplies the MCU This ensures that the I O signal levels of the MCU match the logic levels of the TRF7964A Negative Supply Connections VSS VSS_TX VSS_RX VSS_A VSS_PA The negative supply connections VSS_X of each functional block are all externally connected to GND The substrate connection...

Page 16: ... VDD_X 3 4 V 0B 0 x x x x 0 1 0 VDD_RF 4 5 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 x x x x 0 0 1 VDD_RF 4 4 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 x x x x 0 0 0 VDD_RF 4 3 V VDD_A 3 4 V VDD_X 3 4 V 1 x Don t care Table 6 2 Supply Regulator Setting 3 V System Register Option Bits Setting in Regulator Control Register 1 Address Comments B7 B6 B5 B4 B3 B2 B1 B0 hex Automatic Mode default 0B 1 x x x x x 0 0 Automatic ...

Page 17: ...de 3 Half Power at X 1 31 07 ON ON ON X ON 70 20 5 VDC Mode 4 Full Power at X 1 21 07 ON ON ON X ON 130 23 5 VDC 1 X Don t care Table 6 3 and Table 6 4 show the configuration for the different power modes when using a 3 3 V or 5 V system supply respectively The main reader enable signal is pin EN When EN is set high all of the reader regulators are enabled the 13 56 MHz oscillator is running and t...

Page 18: ...00 The power mode options and states are listed in Table 6 3 When EN is set high or on rising edge of EN2 and then confirmed by EN 1 the supply regulators are activated and the 13 56 MHz oscillator started When the supplies are settled and the oscillator frequency is stable the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13 56 MHz frequency derived from the crystal osc...

Page 19: ...A RSSI register and make the decision if swapping the input signals is preferable or not Setting B3 in Chip Status Control register address 0x00 to 1 connects RX_IN1 pin 8 to the auxiliary received and RX_IN2 pin 9 to the main receiver This mechanism needs to be used to avoid reading holes The main and auxiliary receiver input stages are RF envelope detectors The RF amplitude at RX_IN1 and RX_IN2 ...

Page 20: ...d a data clock The decoder logic is designed for maximum error tolerance This enables the decoder section to successfully decode even partly corrupted subcarrier signals that otherwise would be lost due to noise or interference In the framing logic section the serial bit stream data is formatted in bytes Special signals such as the start of frame SOF end of frame EOF start of communication and end...

Page 21: ...7 76 µs This register is also preset automatically for every new protocol selection The digitized output of the analog receiver is at the input of the digital portion of the receiver This input signal is the subcarrier coded signal which is a digital representation of modulation signal on the RF envelope The digital part of the receiver consists of two sections which partly overlap The first secti...

Page 22: ...6 7 for B0 B4 settings based on ISO protocol used by application Table 6 7 Coding of the ISO Control Register For RFID Mode B5 0 Iso_4 Iso_3 Iso_2 Iso_1 Iso_0 Protocol Remarks 0 0 0 0 0 ISO15693 low bit rate one subcarrier 1 out of 4 0 0 0 0 1 ISO15693 low bit rate one subcarrier 1 out of 256 0 0 0 1 0 ISO15693 high bit rate one subcarrier 1 out of 4 Default for RFID IC 0 0 0 1 1 ISO15693 high bit...

Page 23: ...n TX by the reader This ensures an updated RSSI measurement for each new tag response The Internal RSSI has 7 steps 3 bit with a typical increment of approximately 4 dB The operating range is between 600 mVPP and 4 2 VPP with a typical step size of approximately 600 mV Both Internal Main and Internal Auxiliary RSSI values are stored in the RSSI Levels and Oscillator Status register 0x0F The nomina...

Page 24: ... The 13 56 MHz or 27 12 MHz crystal or oscillator is controlled by the Chip Status Control register 0x00 and the EN and EN2 terminals The oscillator generates the RF frequency for the RF output stage as well as the clock source for the digital section The buffered clock signal is available at pin 27 SYS_CLK for any other external circuits B4 and B5 inside the Modulation and SYS_CLK register 0x09 c...

Page 25: ... power when configured for 3 V automatic operation The ASK modulation depth is controlled by bits B0 B1 and B2 in the Modulator and SYS_CLK Control register 0x09 The ASK modulation depth range can be adjusted between 7 to 30 or 100 OOK External control of the transmit modulation depth is possible by setting the ISO Control register 0x01 to direct mode While operating the TRF7964A in direct mode th...

Page 26: ...ystem should respond by loading the next data packet into the FIFO At the end of a transmit operation the external system MCU is notified by interrupt request IRQ with a flag in IRQ register 0x0C indicating TX is complete example value 0x80 The TX Length registers also support incomplete byte transmission The high two nibbles in register 0x1D and the nibble composed of bits B4 through B7 in regist...

Page 27: ...n for either a digital or analog output B3 0 enables a digital output B3 1 enables an analog output The design of an external power amplifier requires detailed RF knowledge There are also readily designed and certified high power HF reader modules on the market Copyright 2012 2014 Texas Instruments Incorporated Detailed Description 27 Submit Documentation Feedback Product Folder Links TRF7964A ...

Page 28: ...t in Parallel and Serial Interface Connection or Direct Mode Pin Parallel Parallel Direct Mode SPI With SS SPI Without SS 1 DATA_ CLK DATA_CLK DATA_CLK DATA_CLK from master DATA_CLK from master I O_7 A D 7 not used MOSI 2 data in reader in MOSI 2 data in reader in Direct mode data out subcarrier I O_6 A D 6 MISO 3 data out MCU out MISO 3 data out MCU out or bit stream Direct mode strobe bit clock ...

Page 29: ...ss word is sent In continuous address mode Cont mode 1 the first data that follows the address is written or read to from the given address For each additional data the address is incremented by one Continuous mode can be used to write to a block of control registers in a single stream without changing the address for example setup of the predefined standard control registers from the MCU non vola...

Page 30: ...ta x 3 Data x 4 Data x n StopCont Figure 6 8 Continuous Address Register Write Example Starting with Register 0x00 Using SPI With SS Figure 6 9 Continuous Address Register Read Example Starting with Register 0x00 Using SPI With SS 30 Detailed Description Copyright 2012 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links TRF7964A ...

Page 31: ...ss Mode Start Adr x Data x Adr y Data y Adr z Data z StopSgl Figure 6 10 Single Address Register Write Example of Register 0x00 Using SPI With SS Figure 6 11 Single Address Register Read Example of Register 0x00 Using SPI With SS Copyright 2012 2014 Texas Instruments Incorporated Detailed Description 31 Submit Documentation Feedback Product Folder Links TRF7964A ...

Page 32: ...gister For example if 8 bytes are in the FIFO the FIFO counter Register 0x1C has the hexadecimal value of 0x08 binary value of 00001000 A second counter 12 bits wide indicates the number of bytes being transmitted registers 0x1D and 0x1E in a data frame An extension to the transmission byte counter is a 4 bit broken byte counter also provided in register 0x1E bits B0 to B3 Together these counters ...

Page 33: ...he first byte is written into FIFO Figure 6 13 Example of Checking the FIFO Status Register Using SPI With SS 6 10 2 Parallel Interface Mode In parallel mode the start condition is generated on the rising edge of the I O_7 pin while the CLK is high This is used to reset the interface logic Figure 6 14 shows the sequence of the data with an 8 bit address word first followed by data Communication is...

Page 34: ...receiving an IRQ_FIFO or RX complete interrupt the MCU must read the FIFO status register 0x1C to determine the number of bytes to be read from the FIFO Next the MCU must read the data in the FIFO It is optional to read the FIFO status register 0x1C after reading FIFO data to determine if the receive is complete In the case of an IRQ_FIFO the MCU should expect either another IRQ_FIFO or RX complet...

Page 35: ...rupt is sent to inform the MCU that the task is complete 6 10 5 Serial Interface Communication SPI When an SPI interface is used I O pins I O_2 I O_1 and I O_0 must be hard wired according to Table 6 9 On power up the TRF7964A looks for the status of these pins and then enters into the corresponding mode The choice of one of these modes over another should be predicated by the available GPIOs and ...

Page 36: ...ition is when Data Clock is high see Table 6 9 2 Send address word to IRQ status register 0x0C with read and continuous address mode bits set to 1 see Table 6 9 3 Read 1 byte 8 bits from IRQ status register 0x0C 4 Dummy read 1 byte from register 0x0D collision position and interrupt mask 5 Stop the dummy read a When using slave select SS set SS bit high b When not using SS stop condition when Data...

Page 37: ...validated in the reader on the falling edge as shown in Figure 6 19 Communication is terminated when the Slave Select signal goes high All words must be 8 bits long with the MSB transmitted first Figure 6 19 SPI With Slave Select Timing Diagram The read command is sent out on the MOSI pin MSB first in the first eight clock cycles MOSI data changes on the rising edge and is validated in the reader ...

Page 38: ... The TRF7964A takes these bytes from the MCU and then send out Request Flags Inventory Command and Mask over the air to the ISO15693 transponder After these three bytes have been transmitted an interrupt occurs to indicate back to the reader that the transmission has been completed In the example in Figure 6 23 this IRQ occurs approximately 1 6 ms after the SS line goes high after the Inventory co...

Page 39: ... 6 24 the IRQ Status Register is read using method previously recommended followed by a single read of the FIFO status register which indicates that there are 10 bytes to be read out Figure 6 24 Read IRQ Status Register After Inventory Command This is then followed by a continuous read of the FIFO The first byte is and should be 0x00 for no error The next byte is the DSFID usually shipped by manuf...

Page 40: ... is good form to reset the FIFO and then read out the RSSI value of the tag In this case the transponder is very close to the antenna so value of 0x7F is recovered Figure 6 26 Reset FIFO and Read RSSI 40 Detailed Description Copyright 2012 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links TRF7964A ...

Page 41: ... the direct subcarrier signal B6 0 or the serial data of the selected decoder If B6 1 then the user must also define which protocol should be used for bit decoding by writing the appropriate setting in the ISO Control register The reader actually enters the direct mode when B6 direct is set to 1 in the chip status control register Direct mode starts immediately The write command should not be term...

Page 42: ...lation 0x21 for 6 78 MHz Clock and OOK 100 modulation 0x20 for 6 78 MHz Clock and ASK 10 modulation 0x22 for 6 78 MHz Clock and ASK 7 modulation 0x23 for 6 78 MHz Clock and ASK 8 5 modulation 0x24 for 6 78 MHz Clock and ASK 13 modulation 0x25 for 6 78 MHz Clock and ASK 16 modulation See register 0x09 definition for all other possible values Example register setting for ISO14443A at 106 kbps ISO Co...

Page 43: ...ition terminates the Direct Mode and clears bit B6 in the Chip Status Control register 0x00 NOTE Access to Registers FIFO and IRQ is not available during Direct Mode 0 The reader enters the Direct Mode 0 when bit 6 of the Chip Status Control register 0x00 is set to a 1 and stays in Direct Mode 0 until a stop condition is sent from the microcontroller NOTE The write command should not be terminated...

Page 44: ...er sees when using DM0 in an actual application Figure 6 30 is presented to clearly show the relationship between the MOD pin being controlled by the MCU and the resulting modulated 13 56 MHz carrier signal Figure 6 30 TX Sequence Out in DM0 Step 6 Receive Data Using Direct Mode After the TX operation is complete the tag responds to the request and the subcarrier data is available on pin I O_6 The...

Page 45: ... 44 to 3 µs µs TRF7964A www ti com SLOS787H MAY 2012 REVISED APRIL 2014 Figure 6 31 Receive Data Bits and Framing Level Figure 6 32 is presented to clearly show an example of what the developer should expect on the I O_6 line during the RX process while in Direct Mode 0 Copyright 2012 2014 Texas Instruments Incorporated Detailed Description 45 Submit Documentation Feedback Product Folder Links TRF...

Page 46: ... Commands from MCU to Reader 6 12 1 Command Codes Table 6 14 Address and Command Word Bit Distribution Command Code Command Comments 0x00 Idle 0x03 Software Initialization Same as Power on Reset 0x0F Reset 0x10 Transmission without CRC 0x11 Transmission with CRC 0x12 Delayed Transmission without CRC 0x13 Delayed Transmission with CRC 0x14 End of Frame Transmit Next Time Slot ISO15693 0x16 Block Re...

Page 47: ...n initialize transmission enable reader and turn reader on or off 6 12 1 1 Idle 0x00 This command issues dummy clock cycles In parallel mode one cycle is issued In SPI mode eight cycles are issued 6 12 1 2 Software Initialization 0x03 This command starts a Power on Reset After sending this command the register values change as shown in Table 6 16 Table 6 16 Register Values After Sending Software I...

Page 48: ...sion Without CRC 0x12 Same as Section 6 12 1 6 with CRC excluded 6 12 1 8 Transmit Next Time Slot 0x14 When this command is received the reader transmits the next slot command The next slot sign is defined by the protocol selection 6 12 1 9 Block Receiver 0x16 The block receiver command puts the digital part of receiver bit decoder and framer in reset mode This is useful in an extremely noisy envi...

Page 49: ...de 1 2 3 4 5 6 7 Binary Code 001 010 011 001 101 011 111 6 12 1 12 Test External RF RSSI at RX Input with TX OFF 0x19 This command can be used in active mode when the RF receiver is switched on but RF output is switched off This means bit B1 1 in Chip Status Control Register The level of RF signal received on the antenna is measured and displayed in the RSSI Levels register 0x0F The relation betwe...

Page 50: ... to 0x0B are automatically configured to the new protocol parameters After selecting the protocol it is possible to change some low level register contents if needed However changing to another protocol and then back reloads the default settings and so then the custom settings must be reloaded The Clo0 and Clo1 register 0x09 bits which define the microcontroller frequency available on the SYS_CLK ...

Page 51: ...st Registers 0x1A Test Register Preset 0x00 R W 0x1B Test Register Preset 0x00 R W FIFO Registers 0x1C FIFO status R 0x1D TX length byte 1 R W 0x1E TX length byte 2 R W 0x1F FIFO I O register R W Copyright 2012 2014 Texas Instruments Incorporated Detailed Description 51 Submit Documentation Feedback Product Folder Links TRF7964A ...

Page 52: ...put RX_IN1 input is used 1 AGC on Enables AGC AGC gain can be set in register 0x0A B2 agc_on 0 AGC off AGC block is disabled 1 Receiver activated for Forced enabling of receiver and TX oscillator Used for external field external field measurement measurement B1 rec_on 0 Automatic Enable Allows enable of the receiver by Bit 5 of this register 0x00 1 5 V operation B0 vrs5_3 Selects the VIN voltage r...

Page 53: ...bcarrier 1 out of 4 0 0 1 0 1 ISO15693 low bit rate 6 67 kbps double subcarrier 1 out of 256 0 0 1 1 0 ISO15693 high bit rate 26 69 kbps double subcarrier 1 out of 4 ISO15693 high bit rate 26 69 kbps double subcarrier 0 0 1 1 1 1 out of 256 0 1 0 0 0 ISO14443A RX bit rate 106 kbps RX bit rate 1 0 1 0 0 1 ISO14443A RX high bit rate 212 kbps 0 1 0 1 0 ISO14443A RX high bit rate 424 kbps 0 1 0 1 1 IS...

Page 54: ...l_egt 0 EGT after last byte is omitted B0 Reserved 6 13 3 2 2 ISO14443 High Bit Rate and Parity Options Register 0x03 Table 6 24 ISO14443 High Bit Rate and Parity Options Register 0x03 Function Selects the ISO subsets for ISO14443 TX Default 0x00 at POR H or EN L and at each write to ISO Control register Bit Name Function Description TX bit rate different from RX B7 dif_tx_br Valid for ISO14443A B...

Page 55: ...Timer Length B0 tm_length8 Timer Length LSB 6 13 3 2 4 TX Timer Low Byte Control Register 0x05 Table 6 26 TX Timer Low Byte Control Register 0x05 Function For Timings Default 0x00 at POR H or EN L and at each write to ISO Control register Bit Name Function Description B7 tm_length7 Timer Length MSB B6 tm_length6 Timer Length Defines the time when delayed transmission is started B5 tm_length5 Timer...

Page 56: ...3 3 2 6 RX No Response Wait Time Register 0x07 The RX No Response timer is controlled by the RX NO Response Wait Time Register 0x07 This timer measures the time from the start of slot in the anticollision sequence until the start of tag response If there is no tag response in the defined time an interrupt request is sent and a flag is set in IRQ status control register 0x0C This enables the extern...

Page 57: ... 6 29 RX Wait Time Register 0x08 Function Defines the time after TX EOF when the RX input is disregarded for example to block out electromagnetic disturbance generated by the responding card Default 0x1F at POR H or EN L and at each write toISO control register Bit Name Function Description B7 Rxw7 Defines the time after the TX EOF during which the RX input is ignored Time B6 Rxw6 starts from the ...

Page 58: ...Clo1 and Clo0 Bit Name Function Description B7 27MHz Enables 27 12 MHz crystal Default 1 enabled Enable ASK OOK pin pin 12 for on the fly change between any preselected 1 Enables external ASK modulation as defined by B0 to B2 and OOK modulation selection of ASK or OOK B6 en_ook_p modulation If B6 is 1 pin 12 is configured as follows 0 Default operation as 1 OOK modulation defined in B0 to B2 0x09 ...

Page 59: ...nominal gain of 15 and the 3 dB band pass frequencies are adjustable in the range from 100 kHz to 400 kHz for high pass and 600 kHz to 1 5 MHz for low pass The next gain and filtering stage has a nominal gain of 8 and the frequency characteristic identical to first stage The filter setting is done automatically with internal preset for each new selection of communication standard in ISO Control re...

Page 60: ...4 V see Table 6 33 and B1 vrs1 set LSB Table 6 34 B0 vrs0 Table 6 33 Supply Regulator Setting Manual 5 V System Option Bits Setting in Control Register Register Action B7 B6 B5 B4 B3 B2 B1 B0 00 1 5 V system 0B 0 Manual regulator setting 0B 0 1 1 1 VDD_RF 5 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 1 1 0 VDD_RF 4 9 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 1 0 1 VDD_RF 4 8 V VDD_A 3 4 V VDD_X 3 4 V 0B 0 1 0 0 VDD_RF 4 ...

Page 61: ...et due to RX start start of RX but the interrupt request IRQ 1 is sent when RX is finished Signals FIFO high or low as set in the Adjustable FIFO IRQ Levels 0x14 B5 Irq_fifo Signals the FIFO level register Indicates receive CRC error only if B7 no RX CRC of ISO Control register is B4 Irq_err1 CRC error set to 0 B3 Irq_err2 Parity error Indicates parity error for ISO14443A B2 Irq_err3 Byte framing ...

Page 62: ...aming B2 En_irq_err3 Default 1 error or EOF Interrupt enable for collision B1 En_irq_col Default 1 error Enables no response B0 En_irq_noresp Default 0 interrupt Table 6 39 Collision Position Register 0x0E Function Displays the bit position of collision or error Default 0x00 at POR H and EN L Automatically reset after read operation Bit Name Function Description B7 Col7 Bit position of collision M...

Page 63: ...RSSI value is reset during next transmit action of the reader so the new tag response level can be measured The RSSI levels calculated to the RF_IN1 and RF_IN2 are presented in Section 6 5 1 1 and Section 6 5 1 2 The RSSI has 7 steps 3 bits with 4 dB increment The input level is the peak to peak modulation level of RF signal measured on one side envelope positive or negative 6 13 3 3 4 Special Fun...

Page 64: ...6 of the IRQ Status completed Register 0x0C 6 13 3 3 6 Adjustable FIFO IRQ Levels Register 0x14 Table 6 43 Adjustable FIFO IRQ Levels Register 0x14 Function Adjusts level at which FIFO indicates status by IRQ Default 0x00 at POR H and EN L Bit Name Function Description B7 Reserved Reserved B6 Reserved Reserved B5 Reserved Reserved B4 Reserved Reserved B3 Wlh_1 Wlh_1 Wlh_0 IRQ Level 0 0 124 FIFO hi...

Page 65: ...ut and digitizing Second stage gain 6 dB B3 low2 HP corner frequency 2 First stage gain 6 dB HP B2 low1 corner frequency 2 B1 zun Input followers test AGC test AGC level is B0 Test_AGC seen on rssi_210 bits 6 13 3 4 2 Test Register 0x1B Table 6 45 Test Register 0x1B for Test or Direct Use Default 0x00 at POR H and EN L When a test_dec or test_io is set IC is switched to test mode Test Mode persist...

Page 66: ...7 Foverflow FIFO overflow error Bit is set when FIFO has more than 127 bytes presented to it B6 Fb6 FIFO bytes fb 6 B5 Fb5 FIFO bytes fb 5 B4 Fb4 FIFO bytes fb 4 B3 Fb3 FIFO bytes fb 3 B2 Fb2 FIFO bytes fb 2 Bits B0 B6 indicate how many bytes that are in the FIFO to be read out N number of bytes in hex B1 Fb1 FIFO bytes fb 1 B0 Fb0 FIFO bytes fb 0 66 Detailed Description Copyright 2012 2014 Texas ...

Page 67: ...lete byte B0 Txl4 bn 4 Table 6 48 TX Length Byte2 Register 0x1E Function Low nibbles of complete bytes to be transferred through FIFO Information about a broken byte and number of bits to be transferred from it Default 0x00 at POR and EN 0 It is also automatically reset at TX EOF Bit Name Function Description Number of complete byte B7 Txl3 bn 3 Number of complete byte B6 Txl2 bn 2 Low nibble of c...

Page 68: ...nsiderations 7 1 TRF7964A Reader System Using Parallel Microcontroller Interface 7 1 1 General Application Considerations Figure 7 1 shows the most flexible TRF7964A application schematic Both ISO15693 ISO14443 and FeliCa systems can be addressed Due to the low clock frequency on the DATA_CLK line the parallel interface is the most robust way to connect the TRF7964A with the MCU Figure 7 1 shows m...

Page 69: ...System Using SPI With SS Mode 7 2 1 General Application Considerations Figure 7 2 shows the TRF7964A application schematic optimized for both ISO15693 and ISO14443 systems using the Serial Port Interface SPI Short SPI lines proper isolation of radio frequency lines and a proper ground area are essential to avoid interference The recommended clock frequency on the DATA_CLK line is 2 MHz Figure 7 2 ...

Page 70: ...f the crossings are unavoidable 90 crossings should be used to minimize coupling of the lines Depending on the production test plan consider possible implementations of test pads or test vias for use during testing The necessary pads or vias should be placed in accordance with the proposed test plan to enable easy access to those test points If the system implementation is complex for example if t...

Page 71: ...nce Matching Circuit This yields the Smith Chart Simulation shown in Figure 7 4 Figure 7 4 Smith Chart Simulation Copyright 2012 2014 Texas Instruments Incorporated Application Schematic and Layout Considerations 71 Submit Documentation Feedback Product Folder Links TRF7964A ...

Page 72: ...able to avoid damage to equipment Expected output power levels under various operating conditions are shown in Table 6 20 7 5 Reader Antenna Design Guidelines For HF antenna design considerations using the TRF7964A see these documents Antenna Matching for the TRF7960 RFID Reader SLOA135 TRF7960TB HF RFID Reader Module User s Guide SLOU297 72 Application Schematic and Layout Considerations Copyrigh...

Page 73: ...maged by ESD Texas Instruments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtle performance degradation to complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device ...

Page 74: ...der bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Mo...

Page 75: ...UM www ti com 24 Oct 2015 Addendum Page 2 In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis ...

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Page 79: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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