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SLOS787H – MAY 2012 – REVISED APRIL 2014
4.2
Terminal Functions
describes the signals.
Table 4-1. Terminal Functions
TERMINAL
TYPE
(1)
DESCRIPTION
NAME
NO.
V
DD_A
1
OUT
Internal regulated supply (2.7 V to 3.4 V) for analog circuitry
V
IN
2
SUP
External supply input to chip (2.7 V to 5.5 V)
V
DD_RF
3
OUT
Internal regulated supply (2.7 V to 5 V), normally connected to V
DD_PA
(pin 4)
V
DD_PA
4
INP
Supply for PA; normally connected externally to V
DD_RF
(pin 3)
TX_OUT
5
OUT
RF output (selectable output power, 100 mW or 200 mW, with V
DD
= 5 V)
V
SS_PA
6
SUP
Negative supply for PA; normally connected to circuit ground
V
SS_RX
7
SUP
Negative supply for RX inputs; normally connected to circuit ground
RX_IN1
8
INP
Main RX input
RX_IN2
9
INP
Auxiliary RX input
V
SS
10
SUP
Chip substrate ground
BAND_GAP
11
OUT
Bandgap voltage (V
BG
= 1.6 V); internal analog voltage reference
Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for Direct Mode 0 or 1.
ASK/OOK
12
BID
Can be configured as an output to provide the received analog signal output.
IRQ
13
OUT
Interrupt request
INP
External data modulation input for Direct Mode 0 or 1
MOD
14
OUT
Subcarrier digital data output (see registers 0x1A and 0x1B)
V
SS_A
15
SUP
Negative supply for internal analog circuits; connected to GND
V
DD_I/O
16
INP
Supply for I/O communications (1.8 V to V
IN
) level shifter. V
IN
should be never exceeded.
I/O_0
17
BID
I/O pin for parallel communication
I/O_1
18
BID
I/O pin for parallel communication
I/O pin for parallel communication
I/O_2
19
BID
TX Enable (in Special Direct Mode)
I/O pin for parallel communication
I/O_3
20
BID
TX Data (in Special Direct Mode)
I/O pin for parallel communication
I/O_4
21
BID
Slave Select signal in SPI mode
I/O pin for parallel communication
I/O_5
22
BID
Data clock output in Direct Mode 1 and Special Direct Mode
I/O pin for parallel communication
I/O_6
23
BID
MISO for serial communication (SPI)
Serial bit data output in Direct Mode 1 or subcarrier signal in Direct Mode 0
I/O pin for parallel communication.
I/O_7
24
BID
MOSI for serial communication (SPI)
Selection of power down mode. If EN2 is connected to V
IN
, then V
DD_X
is active during power
EN2
25
INP
down mode 2 (for example, to supply the MCU).
DATA_CLK
26
INP
Data Clock input for MCU communication (parallel and serial)
If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal
that is used, options are as follows (see register 0x09):
SYS_CLK
27
OUT
13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz
27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz
If EN = 0 and EN2 = 1, then system clock is set to 60 kHz
EN
28
INP
Chip enable input (If EN = 0, then chip is in sleep or power-down mode).
V
SS_D
29
SUP
Negative supply for internal digital circuits
(1)
SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output
Copyright © 2012–2014, Texas Instruments Incorporated
Terminal Configuration and Functions
7
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