N2HET1
N2HET2
ePWM1
2 VCLK4 cycles
Pulse Stretch
EPWM1SYNCI
SYNCI
EXT_LOOP_SYNC
N2HET1_LOOP_SYNC
double
sync
6 VCLK4
Cycles Filter
PINMMR36[25]
PINMMR47[8,9,10]
98
TMS570LS0714
SPNS226E – JUNE 2013 – REVISED NOVEMBER 2016
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TMS570LS0714
Peripheral Information and Electrical Specifications
Copyright © 2013–2016, Texas Instruments Incorporated
7.2.1
ePWM Clocking and Reset
Each ePWM module has a clock enable (EPWMxENCLK). When SYS_nRST is active-low, the clock
enables are ignored and the ePWM logic is clocked so that it can reset to a proper state. When
SYS_nRST goes in-active high, the state of clock enable is respected.
Table 7-5. ePWMx Clock Enable Control
ePWM MODULE INSTANCE
CONTROL REGISTER TO
ENABLE CLOCK
DEFAULT VALUE
ePWM1
PINMMR37[8]
1
ePWM2
PINMMR37[16]
1
ePWM3
PINMMR37[24]
1
ePWM4
PINMMR38[0]
1
ePWM5
PINMMR38[8]
1
ePWM6
PINMMR38[16]
1
ePWM7
PINMMR38[24]
1
The default value of the control registers to enable the clocks to the ePWMx modules is 1. This means
that the VCLK4 clock connections to the ePWMx modules are enabled by default. The application can
choose to gate off the VCLK4 clock to any ePWMx module individually by clearing the respective control
register bit.
7.2.2
Synchronization of ePWMx Time-Base Counters
A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM
module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The
input synchronization for the first instance (ePWM1) comes from an external pin.
Figure 7-3
shows the
synchronization connections for all the ePWMx modules. Each ePWM module can be configured to use or
ignore the synchronization input. For more information, see the ePWM chapter in the device-specific
Technical Reference Manual (TRM).
7.2.3
Synchronizing all ePWM Modules to the N2HET1 Module Time Base
The connection between the N2HET1_LOOP_SYNC and SYNCI input of ePWM1 module is implemented
as shown in
Figure 7-5
.
Figure 7-5. Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules