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TMS570LS0714
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SPNS226E – JUNE 2013 – REVISED NOVEMBER 2016
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TMS570LS0714
System Information and Electrical Specifications
Copyright © 2013–2016, Texas Instruments Incorporated
Table 6-31. ESM Channel Assignments (continued)
ERROR CONDITION
GROUP
CHANNELS
MibSPI1 - RAM parity error
Group1
17
MibSPI3 - RAM parity error
Group1
18
MibADC1 - RAM parity error
Group1
19
Reserved
Group1
20
DCAN1 - RAM parity error
Group1
21
DCAN3 - RAM parity error
Group1
22
DCAN2 - RAM parity error
Group1
23
MibSPI5 - RAM parity error
Group1
24
Reserved
Group1
25
RAM even bank (B0TCM) - correctable ECC error
Group1
26
CPU - self-test failed
Group1
27
RAM odd bank (B1TCM) - correctable ECC error
Group1
28
Reserved
Group1
29
DCC1 - error
Group1
30
CCM-R4 - self-test failed
Group1
31
Reserved
Group1
32
Reserved
Group1
33
N2HET2 - RAM parity error
Group1
34
FMC - correctable ECC error (Bank 7 access)
Group1
35
FMC - uncorrectable ECC error (Bank 7 access)
Group1
36
IOMM - Access to unimplemented location in IOMM frame, or write access
detected in unprivileged mode
Group1
37
Power domain controller compare error
Group1
38
Power domain controller self-test error
Group1
39
eFuse Controller Error – this error signal is generated when any bit in the eFuse
controller error status register is set. The application can choose to generate an
interrupt whenever this bit is set to service any eFuse controller error conditions.
Group1
40
eFuse Controller - Self-Test Error. This error signal is generated only when a self-
test on the eFuse controller generates an error condition. When an ECC self-test
error is detected, group 1 channel 40 error signal will also be set.
Group1
41
Reserved
Group1
42
Reserved
Group1
43
Reserved
Group1
44
Reserved
Group1
45
Reserved
Group1
46
Reserved
Group1
47
Reserved
Group1
48
Reserved
Group1
49
Reserved
Group1
50
Reserved
Group1
51
Reserved
Group1
52
Reserved
Group1
53
Reserved
Group1
54
Reserved
Group1
55
Reserved
Group1
56
Reserved
Group1
57
Reserved
Group1
58
Reserved
Group1
59
Reserved
Group1
60