V
CCIO
V
IH
V
IH
V
IL
0
Input
t
pw
V
IL
93
TMS570LS0714
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SPNS226E – JUNE 2013 – REVISED NOVEMBER 2016
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TMS570LS0714
Peripheral Information and Electrical Specifications
Copyright © 2013–2016, Texas Instruments Incorporated
(1)
t
c(VCLK)
= peripheral VBUS clock cycle time = 1 / f
(VCLK)
(2)
The timing shown above is only valid for pin used in general-purpose input mode.
7
Peripheral Information and Electrical Specifications
7.1
I/O Timings
7.1.1
Input Timings
Figure 7-1. TTL-Level Inputs
Table 7-1. Timing Requirements for Inputs
(1)
MIN
MAX
UNIT
t
pw
Input minimum pulse width
t
c(VCLK)
+ 10
(2)
ns
t
in_slew
Time for input signal to go from V
IL
to V
IH
or from V
IH
to V
IL
1
ns
7.1.2
Output Timings
Table 7-2. Switching Characteristics for Output Timings versus Load Capacitance (C
L
)
PARAMETER
MIN
MAX
UNIT
Rise time, t
r
8 mA low-EMI pins
(see
Table 4-40
)
CL = 15 pF
2.5
ns
CL = 50 pF
4
CL = 100 pF
7.2
CL = 150 pF
12.5
Fall time, t
f
CL = 15 pF
2.5
CL = 50 pF
4
CL = 100 pF
7.2
CL = 150 pF
12.5
Rise time, t
r
4 mA low-EMI pins
(see
Table 4-40
)
CL = 15 pF
5.6
ns
CL = 50 pF
10.4
CL = 100 pF
16.8
CL = 150 pF
23.2
Fall time, t
f
CL = 15 pF
5.6
CL= 50 pF
10.4
CL = 100 pF
16.8
CL = 150 pF
23.2
Rise time, t
r
2 mA-z low-EMI pins
(see
Table 4-40
)
CL = 15 pF
8
ns
CL = 50 pF
15
CL = 100 pF
23
CL = 150 pF
33
Fall time, t
f
CL = 15 pF
8
CL = 50 pF
15
CL = 100 pF
23
CL = 150 pF
33
