TCM BUS
TCM BUS
72-bit data + ECC
72-bit data + ECC
Upper 32-bits data
and 4 ECC bits
Lower 32-bits data
and 4 ECC bits
36 Bit
wide
RAM
36 Bit
36-bit-wide
RAM
36 Bit
wide
RAM
36 Bit
RAM
Upper 32-bits data
and 4 ECC bits
Lower 32-bits data
and 4 ECC bits
36 Bit
wide
RAM
36 Bit
36 Bit
wide
RAM
36 Bit
wide
RAM
TCRAM
Interface 1
Cortex R4
)Œ
B0
TCM
B1
TCM
TCRAM
Interface 2
36-bit-wide
RAM
36-bit-wide
RAM
36-bit-wide
RAM
69
TMS570LS0714
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SPNS226E – JUNE 2013 – REVISED NOVEMBER 2016
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System Information and Electrical Specifications
Copyright © 2013–2016, Texas Instruments Incorporated
6.11 Tightly Coupled RAM Interface Module
Figure 6-10
shows the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F™ CPU.
Figure 6-10. TCRAM Block Diagram
6.11.1 Features
The features of the Tightly Coupled RAM (TCRAM) Module are:
•
Acts as slave to the BTCM interface of the Cortex-R4F CPU
•
Supports CPU internal ECC scheme by providing 64-bit data and 8-bit ECC code
•
Monitors CPU Event Bus and generates single-bit or multibit error interrupts
•
Stores addresses for single-bit and multibit errors
•
Supports RAM trace module
•
Provides CPU address bus integrity checking by supporting parity checking on the address bus
•
Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
•
Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks
and generating independent RAM access control signals to the two banks
•
Supports auto-initialization of the RAM banks along with the ECC bits
6.11.2 TCRAMW ECC Support
The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. The
TCRAMW also stores the ECC port contents of the CPU in the ECC RAM when the CPU does a write to
the RAM. The TCRAMW monitors the CPU event bus and provides registers for indicating single-bit or
multibit errors and also for identifying the address that caused the single or multi-bit error. The event
signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.
For more information, see the device-specific Technical Reference Manual.
6.12
Parity Protection for Accesses to Peripheral RAMs
Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the
parity is calculated based on the data read from the peripheral RAM and compared with the good parity
value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates
a parity error signal that is mapped to the Error Signaling Module. The module also captures the
peripheral RAM address that caused the parity error.
