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TMS570LS0714

SPNS226E – JUNE 2013 – REVISED NOVEMBER 2016

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9.10.2 LIN Certification

9.10.2.1 LIN Master Mode

Figure 9-4. LIN Certification - Master Mode

Summary of Contents for TMS570LS0714

Page 1: ...Checker CRC Direct Memory Access DMA Controller 16 Channels and 32 Peripheral Requests Parity for Control Packet RAM DMA Accesses Protected by Dedicated MPU Frequency Modulated Phase Locked Loop FMPLL...

Page 2: ...Links TMS570LS0714 Device Overview Copyright 2013 2016 Texas Instruments Incorporated 1 2 Applications Electric Power Steering EPS Braking Systems ABS and ESC HEV and EV Inverter Systems Battery Mana...

Page 3: ...apture eCAP modules two Enhanced Quadrature Encoder Pulse eQEP modules and two 12 bit Analog to Digital Converters ADCs supporting up to 24 inputs The N2HET is an advanced intelligent timer that provi...

Page 4: ...tiply the external frequency reference to a higher frequency for internal use The FMPLL provides one of the six possible clock source inputs to the Global Clock Module GCM The GCM manages the mapping...

Page 5: ...gend for Power Domains SYS nPORRST nRST ECLK ESM nERROR 768KB Flash with ECC Switched Central Resource I2C N2HET1 GIO I2C_SCL I2C_SDA GIOB 7 0 GIOA 7 0 N2HET2 18 16 N2HET2 15 0 N2HET1 31 0 N2HET1_PIN_...

Page 6: ...d RAM Interface Module 69 6 12 Parity Protection for Accesses to Peripheral RAMs 69 6 13 On Chip SRAM Initialization and Testing 71 6 14 Vectored Interrupt Manager 73 6 15 DMA Controller 76 6 16 Real...

Page 7: ...Table 4 2 PGE Enhanced High End Timer Modules N2HET Added a description for pins 14 and 55 N2HET1_PIN_nDIS and N2HET2_PIN_nDIS respectively 13 Table 4 20 PZ Enhanced High End Timer Modules N2HET Added...

Page 8: ...6 6 4 3 6 6 4 3 5 6 1 3 5 6 4 2 5 1 1 4 SPI CS 2 2 1 2 2 1 1 1 1 1 1 1 2 SCI LIN 2 1 with LIN 2 1 with LIN 2 1 with LIN 2 1 with LIN 1 with LIN 1 with LIN I2C 1 1 1 1 GPIO INT 120 with 16 interrupt ca...

Page 9: ...1IN 07 AD1IN 18 AD2IN 02 AD1IN 19 AD2IN 03 AD1IN 20 AD2IN 04 AD1IN 21 AD2IN 05 ADREFHI ADREFLO VSSAD VCCAD AD1IN 09 AD2IN 09 AD1IN 01 AD1IN 02 AD1IN 03 AD1IN 11 AD2IN 11 AD1IN 04 AD1IN 12 AD2IN 12 AD1...

Page 10: ...5 66 67 68 69 70 71 72 73 74 75 53 GIOA 3 INT 3 VSS VCCIO GIOA 1 IN T 1 TEST GIOA 7 IN T 7 VSS KELVIN_GN D OSCIN VC C GIOA 6 INT 6 GIOA 5 INT 5 GIOA 2 INT 2 FLTP2 FLTP1 GIOA 0 IN T 0 GIOA 4 INT 4 OSCO...

Page 11: ...cribed For information on how to select between different multiplexed functions see Section 4 3 Pin Multiplexing or see the I O Multiplexing and Control Module IOMM chapter of the TMS570LS09x 07x 16 3...

Page 12: ...Programmable 20 A ADC1 event trigger input or GIO MIBSPI3NCS 0 AD2EVT GIOB 2 EQEP1I N2HET2_PIN_nDIS 55 I O Pullup Programmable 20 A ADC2 event trigger input or GIO AD1IN 0 60 Input None ADC1 analog i...

Page 13: ...39 N2HET1 14 125 N2HET1 15 MIBSPI1NCS 4 ECAP1 41 N2HET1 16 EPWM1SYNCI EPWM1SYNCO 139 MIBSPI1NCS 1 N2HET1 17 EQEP1S 130 Pullup N2HET1 18 EPWM6A 140 Pulldown MIBSPI1NCS 2 N2HET1 19 40 Pullup N2HET1 20 E...

Page 14: ...ure Module 4 I O MIBSPI5NENA MIBSPI5SOMI 1 ECAP5 97 Enhanced Capture Module 5 I O MIBSPI1NCS 0 MIBSPI1SOMI 1 ECAP6 105 Enhanced Capture Module 6 I O 1 These signals are double synchronized and then op...

Page 15: ...A N2HET1 0 SPI4CLK EPWM2B 25 Enhanced PWM2 Output B N2HET1 02 SPI4SIMO 0 EPWM3A 30 Enhanced PWM3 Output A N2HET1 05 SPI4SOMI 0 N2HET2 12 EPWM3B 31 Enhanced PWM3 Output B MIBSPI5NCS 0 EPWM4A 32 Output...

Page 16: ...ng interrupts to the CPU on rising falling both edges GIOA 1 5 GIOA 2 N2HET2 0 EQEPII 9 GIOA 5 EXTCLKIN1 EPWM1A N2HET1_PIN_nDIS 14 GIOA 6 N2HET2 4 EPWM1B 16 GIOA 7 N2HET2 6 EPWM2A 22 GIOB 0 126 GIOB 1...

Page 17: ...ter Integrated Circuit Interface Module I2C Terminal Signal Type Reset Pull State Pull Type Description Signal Name 144 PGE MIBSPI3NCS 2 I2CSDA N2HET1 27 nTZ2 4 I O Pullup Programmable 20 A I2C serial...

Page 18: ...4 Pullup Programmable 20 A MibSPI1 slave out master in or GIO MIBSPI1NCS 0 MIBSPI1SOMI 1 ECAP6 105 MIBSPI3CLK AWM1_EXT_SEL 1 EQEP1A 53 I O Pullup Programmable 20 A MibSPI3 clock or GIO MIBSPI3NCS 0 AD...

Page 19: ...rcuitry indicates any reset condition by driving nRST low The external circuitry can assert a system reset by driving nRST low To ensure that an external reset is not arbitrarily generated TI recommen...

Page 20: ...100 A JTAG test clock TDI 110 Input Pullup JTAG test data in TDO 111 Output Pulldown JTAG test data out TMS 108 Input Pullup JTAG test select 4 2 1 16 Flash Supply and Test Pads Table 4 16 PGE Flash...

Page 21: ...l Type Reset Pull State Pull Type Description Signal Name 144 PGE VCCIO 10 3 3 V Power None Operating supply for I Os VCCIO 26 VCCIO 42 VCCIO 104 VCCIO 120 VCCIO 136 4 2 1 19 Ground Reference for All...

Page 22: ...up N2HET1 18 EPWM6A 98 Pulldown MIBSPI1nCS 2 N2HET1 19 27 Pullup MIBSPI1nCS 3 N2HET1 21 39 N2HET1 22 11 Pulldown MIBSPI1nENA N2HET1 23 ECAP4 68 Pullup N2HET1 24 MIBSPI1nCS 5 64 Pulldown MIBSPI3nENA MI...

Page 23: ...2HET2 0 EQEP2I 5 Pulldown Enhanced QEP2 Index 4 2 2 4 Enhanced Pulse Width Modulator Modules ePWM Table 4 23 PZ Enhanced Pulse Width Modulator Modules ePWM TERMINAL SIGNAL TYPE RESET PULL STATE PULL T...

Page 24: ...ising falling both edges GIOA 1 INT 1 2 GIOA 2 INT 2 N2HET2 0 EQEP2I 5 GIOA 3 INT 3 N2HET2 2 8 GIOA 4 INT 4 9 GIOA 5 INT 5 EXTCLKIN EPWM1A N2HET1_PIN_nDIS 10 GIOA 6 INT 6 N2HET2 4 EPWM1B 12 GIOA 7 INT...

Page 25: ...ock or GPIO N2HET1 2 SPI4SIMO EPWM3A 22 SPI2 Slave In Master Out or GPIO 4 2 2 8 Multibuffered Serial Peripheral Interface MibSPI1 and MibSPI3 Table 4 27 PZ Multibuffered Serial Peripheral Interface M...

Page 26: ...tate Pull Type Description Signal Name 100 PZ MibADC1 AD1EVT 58 I O Pulldown Programmable 20 A ADC1 Event Trigger or GPIO AD1IN 0 42 Input Analog Inputs AD1IN 1 49 AD1IN 2 51 AD1IN 3 52 AD1IN 4 54 AD1...

Page 27: ...A The external circuitry can assert a system reset by driving nRST low To ensure that an external reset is not arbitrarily generated TI recommends that an external pullup resistor is connected to thi...

Page 28: ...upply and Test Pads Table 4 33 PZ Flash Supply and Test Pads Terminal Signal Type Reset Pull State Pull Type Description Signal Name 100 PZ VCCP 96 3 3 V Power Flash external pump voltage 3 3 V This t...

Page 29: ...nd Reference This is a single ground reference for all supplies except for the ADC Supply VSS 17 VSS 20 VSS 29 VSS 33 VSS 59 VSS 72 VSS 86 VSS 87 VSS 100 4 3 Pin Multiplexing This microcontroller has...

Page 30: ...1 23 12 17 ECAP4 12 20 53 MIBSPI3CLK 33 24 AWM1_EXT_SEL 1 33 25 EQEP1A 33 26 55 MIBSPI3NCS 0 9 16 AD2EVT 9 17 GIOB 2 9 18 EQEP1I 9 19 37 MIBSPI3NCS 1 7 8 N2HET1 25 7 9 4 MIBSPI3NCS 2 0 24 I2C_SDA 0 25...

Page 31: ...N2HET1 09 6 16 N2HET2 16 6 17 EPWM7A 6 20 118 N2HET1 10 17 0 nTZ3 17 4 6 N2HET1 11 1 8 MIBSPI3NCS 4 1 9 N2HET2 18 1 10 EPWM1SYNCO 1 13 124 N2HET1 12 17 16 39 N2HET1 13 8 0 SCITX 8 1 EPWM5B 8 2 125 N2...

Page 32: ...4 3 17 EPWM1B 3 18 18 GIOA 7 INT 7 4 0 N2HET2 6 4 1 EPWM2A 4 2 73 MIBSPI1NCS 0 13 24 MIBSPI1SOMI 1 13 25 ECAP6 13 28 93 MIBSPI1NCS 1 20 16 N2HET1 17 20 17 EQEP1S 20 20 27 MIBSPI1NCS 2 8 8 N2HET1 19 8...

Page 33: ...Functions Copyright 2013 2016 Texas Instruments Incorporated 4 3 2 Multiplexing of Inputs Some signals are connected to more than one terminal the inputs for these signals can come from any of the ter...

Page 34: ...T1 or BIT1 and BIT2 1 BIT1 and not BIT2 1 N2HET1 27 4 PINMUX0 26 PINMUX25 24 not BIT1 or BIT1 and BIT2 1 BIT1 and not BIT2 1 N2HET1 29 3 PINMUX0 18 PINMUX26 0 not BIT1 or BIT1 and BIT2 1 BIT1 and not...

Page 35: ...PWM4B EPWM5A EPWM5B EPWM6A EPWM6B EPWM7A EPWM7B 4mA TEST MIBSPI3SOMI MIBSPI3SIMO MIBSPI3CLK MIBSPI1SIMO MIBSPI1SOMI MIBSPI1CLK ECAP2 ECAP3 nRST 2mA zero dominant AD1EVT CAN1RX CAN1TX CAN2RX CAN2TX CAN...

Page 36: ...l pins except AD1IN 23 0 or AD2IN 15 0 20 20 mA IIK VI 0 or VI VCCAD AD1IN 23 0 or AD2IN 15 0 10 10 Total 40 40 Output clamp current IOK VO 0 or VO VCCIO All pins except AWM1_EXT_x 20 20 mA Total 40 4...

Page 37: ...TIONS MIN NOM MAX UNIT VCC Digital logic supply voltage Core 1 14 1 2 1 32 V VCCIO Digital logic supply voltage I O 3 3 3 3 6 V VCCAD MibADC supply voltage 3 5 25 V VCCP Flash pump supply voltage 3 3...

Page 38: ...UNIT VOL Low level output voltage IOL IOLmax 0 2VCCIO V IOL 50 A standard output mode 0 2 IOL 50 A low EMI output mode see Section 7 1 2 1 0 2VCCIO VOH High level output voltage IOH IOHmax 0 8VCCIO V...

Page 39: ...s 126 0 005 e0 024 T JK 4 LBIST and PBIST currents are for a short duration typically less than 10 ms They are usually ignored for thermal calculations for the device and the voltage regulator 5 6 Pow...

Page 40: ...FP PZ mechanical package Table 5 1 Thermal Resistance Characteristics PGE Package C W R JA Junction to free air thermal resistance still air using JEDEC 2S2P test board 37 5 R JB Junction to board the...

Page 41: ...e 5 3 Clock Domain Timing Specifications PARAMETER DESCRIPTION CONDITIONS MIN MAX UNIT fHCLK HCLK System clock frequency PZ Pipeline mode enabled 100 MHz Pipeline mode disabled 45 PGE Pipeline mode en...

Page 42: ...2013 REVISED NOVEMBER 2016 www ti com Submit Documentation Feedback Product Folder Links TMS570LS0714 Specifications Copyright 2013 2016 Texas Instruments Incorporated 5 8 1 2 Wait States Required PG...

Page 43: ...rs the core supply VCC and the I O supply VCCIO The other supplies are not monitored by the VMON For example if the VCCAD or VCCP are supplied from a source different from that for VCCIO then there is...

Page 44: ...he power up sequence starts with the I O voltage rising above the minimum I O supply threshold see Table 6 4 for more details core voltage rising above the minimum core supply threshold and the releas...

Page 45: ...evel when nPORRST must remain active during power up and become active during power down 1 14 V VCCIOPORL VCCIO VCCP low supply level when nPORRST must be active during power up 1 1 V VCCIOPORH VCCIO...

Page 46: ...s an internal pullup 6 4 1 Causes of Warm Reset Table 6 5 Causes of Warm Reset DEVICE EVENT SYSTEM STATUS FLAG Power Up Reset Exception Status Register bit 15 Oscillator fail Global Status Register bi...

Page 47: ...ing memories ARMv7 R architecture Memory Protection Unit MPU with 12 regions Dual core logic for fault detection in safety critical applications An L2 memory interface Single 64 bit master AXI interfa...

Page 48: ...ring for each CPU Figure 6 3 Dual CPU Orientation 6 5 4 Duplicate Clock Tree After GCLK The CPU clock domain is split into two clock trees one for each CPU with the clock of the second CPU running at...

Page 49: ...equence for CPU Self Test 1 Configure clock domain frequencies 2 Select number of test intervals to be run 3 Configure the time out period for the self test run 4 Enable self test 5 Wait for CPU reset...

Page 50: ...tion and Electrical Specifications Copyright 2013 2016 Texas Instruments Incorporated Table 6 7 CPU Self Test Coverage continued INTERVALS TEST COVERAGE STCCLK CYLCES 13 86 67 17745 14 87 16 19110 15...

Page 51: ...isabled 2 Reserved Reserved Disabled 3 EXTCLKIN1 External clock input 1 Disabled 4 LFLPO Low frequency output of internal reference oscillator Enabled 5 HFLPO High frequency output of internal referen...

Page 52: ...IH Pulse duration OSCIN high when input to the OSCIN is a square wave 15 ns 6 6 1 2 Low Power Oscillator The Low Power Oscillator LPO is comprised of two oscillators HF LPO and LF LPO in a single macr...

Page 53: ...900 s 10 s Cold start up time 900 s LPO LF oscillator Untrimmed frequency 36 85 180 kHz Start up time from STANDBY LPO BIAS_EN high for at least 900 s 100 s Cold start up time 2000 s 6 6 1 3 Phase Lo...

Page 54: ...t is used to select an available clock source for each clock domain Table 6 13 Clock Domain Descriptions CLOCK DOMAIN DEFAULT SOURCE SOURCE SELECTION REGISTER SPECIAL CONSIDERATIONS HCLK OSCIN GHVSRC...

Page 55: ...DOMAIN DEFAULT SOURCE SOURCE SELECTION REGISTER SPECIAL CONSIDERATIONS VCLKA1 VCLK VCLKASRC Defaults to VCLK as the source Is disabled through the CDDISx registers bit 4 RTICLK VCLK RCLKSRC Defaults t...

Page 56: ...m modules the frequency at this node must not exceed the maximum HCLK specification 1 2 256 I2C I2C baud rate NTU 1 NTU 0 NTU 2 NTU 3 RTI Reserved Reserved Reserved EXTCLKIN 1 Prop_seg DCANx VCLK2 to...

Page 57: ...k Test Mode Options SEL_ECP_PIN CLKTEST 4 0 SIGNAL ON ECLK SEL_GIO_PIN CLKTEST 11 8 SIGNAL ON N2HET1 12 00000 Oscillator 0000 Oscillator Valid Status 00001 Main PLL free running clock output 0001 Main...

Page 58: ...7 3 Dual Clock Comparators The Dual Clock Comparator DCC module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources counter 0 and counter 1 If...

Page 59: ...llator OSCIN 0x5 High frequency LPO 0xA Test clock TCK Table 6 16 DCC1 Counter 1 Clock Sources KEY 3 0 CLOCK SOURCE 3 0 CLOCK NAME Others N2HET1 31 0x0 Main PLL free running clock output 0x1 Reserved...

Page 60: ...also generating a valid reset signal to the CPU 6 8 Glitch Filters A glitch filter is present on the following signals Table 6 19 Glitch Filter Timing Specifications PIN PARAMETER MIN MAX UNIT nPORRST...

Page 61: ...FF 0xFC000000 0xFCFFFFFF 0x20000000 Flash ECC OTP and EEPROM Emulation accesses 61 TMS570LS0714 www ti com SPNS226E JUNE 2013 REVISED NOVEMBER 2016 Submit Documentation Feedback Product Folder Links T...

Page 62: ...F010_0000 0xF013_FFFF 256KB 8KB Bank 7 0xF020_0000 0xF03F_FFFF 2MB 64KB Flash Data Space ECC 0xF040_0000 0xF04F_FFFF 1MB 128KB SCR5 Enhanced Timer Peripherals ePWM1 0xFCF7_8C00 0xFCF7_8CFF 256B 256B A...

Page 63: ...es to unimplemented address offsets lower than 0x3FFF Abort generated for accesses beyond 0x3FFF N2HET2 TU2 RAM PCS 38 0xFF4C_0000 0xFF4D_FFFF 128KB 1KB Abort N2HET1 TU1 RAM PCS 39 0xFF4E_0000 0xFF4F_...

Page 64: ...00 0xFFFF_EBFF 512B 512B Reads return zeros writes have no effect DCC1 PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B Reads return zeros writes have no effect DMA PPS4 0xFFFF_F000 0xFFFF_F3FF 1KB 1KB Reads re...

Page 65: ...s2 Interface OTP ECC Bank 7 Non CPU Accesses to Program Flash and CPU Data RAM CRC Slave Interfaces Peripheral Control Registers All Peripheral Memories And All System Module Control Registers And Mem...

Page 66: ...or erasing the flash banks Flash Module Interface circuitry required between the host CPU and the flash banks and pump module Table 6 22 Flash Memory Banks and Sectors MEMORY ARRAYS OR BANKS SECTOR N...

Page 67: ...a fetched from the flash memory The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module A single bit error is corrected an...

Page 68: ...gramming time 1 40 C to 125 C 8 s 0 C to 60 C for first 25 cycles 2 4 s terase bank0 Sector Bank erase time 2 40 C to 125 C 0 03 4 s 0 C to 60 C for first 25 cycles 16 100 ms twec Write erase cycles w...

Page 69: ...the address bus Performs redundant address decoding for the RAM bank chip select and ECC select generation logic Provides enhanced safety for the RAM addressing by implementing two 36 bit wide byte i...

Page 70: ...struments Incorporated The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application Each individual peripheral contains control registers to enable the pa...

Page 71: ...TYPE Test Pattern Algorithm TRIPLE READ SLOW READ TRIPLE READ FAST READ MARCH 13N 1 TWO PORT cycles MARCH 13N 1 SINGLE PORT cycles ALGO MASK 0x1 ALGO MASK 0x2 ALGO MASK 0x4 ALGO MASK 0x8 PBIST_ROM 1...

Page 72: ...program the memory arrays with error detection capability to a known state based on their error detection scheme odd even parity or ECC The MINITGCR register enables the memory initialization sequenc...

Page 73: ...are dispatch mechanisms when the CPU VIC port is not used Index interrupt Register vectored interrupt Parity protected vector interrupt table against soft errors 6 14 2 Interrupt Request Assignments T...

Page 74: ...rrupt 42 DCAN1 DCAN1 IF3 interrupt 44 DCAN3 DCAN3 level 0 interrupt 45 DCAN2 DCAN2 IF3 interrupt 46 FPU FPU interrupt 47 Reserved Reserved 48 SPI4 SPI4 level 0 interrupt 49 MIBADC2 MibADC2 event group...

Page 75: ...ePWM5INTn ePWM5 Interrupt 98 ePWM5TZINTn ePWM5 Trip Zone Interrupt 99 ePWM6INTn ePWM6 Interrupt 100 ePWM6TZINTn ePWM6 Trip Zone Interrupt 101 ePWM7INTn ePWM7 Interrupt 102 ePWM7TZINTn ePWM7 Trip Zone...

Page 76: ...ata memories Restructure portions of internal data memory Continually service a peripheral 6 15 1 DMA Features CPU independent data transfer One 64 bit master port that interfaces to the TMS570 Memory...

Page 77: ...5 MIBSPI3 5 DCAN2 IF1 DMAREQ 9 MIBADC1 I2C MIBSPI5 MIBADC1 G1 I2C receive MIBSPI5 4 DMAREQ 10 MIBADC1 I2C MIBSPI5 MIBADC1 G2 I2C transmit MIBSPI5 5 DMAREQ 11 RTI MIBSPI1 MIBSPI3 RTI DMAREQ0 MIBSPI1 6...

Page 78: ...g system The timers also let you benchmark certain areas of code by reading the values of the counters at the beginning and the end of the desired code range and calculating the difference between the...

Page 79: ...ating the RTI time bases The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the system module at address 0xFFFFFF50 The default source for RTI1CLK is VC...

Page 80: ...Assignments The ESM integrates all the device error conditions and groups them in the order of severity Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest...

Page 81: ...FMC uncorrectable ECC error Bank 7 access Group1 36 IOMM Access to unimplemented location in IOMM frame or write access detected in unprivileged mode Group1 37 Power domain controller compare error G...

Page 82: ...rved Group2 9 RAM even bank B0TCM address bus parity error Group2 10 Reserved Group2 11 RAM odd bank B1TCM address bus parity error Group2 12 Reserved Group2 13 Reserved Group2 14 Reserved Group2 15 T...

Page 83: ...nts continued ERROR CONDITION GROUP CHANNELS Reserved Group3 10 Reserved Group3 11 Reserved Group3 12 Reserved Group3 13 Reserved Group3 14 Reserved Group3 15 Reserved Group3 16 Reserved Group3 17 Res...

Page 84: ...CM odd uncorrectable error that is redundant address decode User Privilege ESM NMI nERROR 2 8 B1 TCM odd address bus parity error User Privilege ESM NMI nERROR 2 12 FLASH WITH CPU BASED ECC FMC correc...

Page 85: ...ESM 1 23 DCAN3 memory parity error User Privilege ESM 1 22 PLL PLL slip error User Privilege ESM 1 10 CLOCK MONITOR Clock monitor interrupt User Privilege ESM 1 11 DCC DCC1 error User Privilege ESM 1...

Page 86: ...Information and Electrical Specifications Copyright 2013 2016 Texas Instruments Incorporated Table 6 32 Reset Abort Error Sources continued ERROR SOURCE CPUMODE ERROR RESPONSE ESM HOOKUP GROUP CHANNE...

Page 87: ...as Instruments Incorporated 6 19 Digital Windowed Watchdog This device includes a Digital Windowed Watchdog DWWD module that protects against runaway code execution see Figure 6 13 The DWWD module all...

Page 88: ...version C to allow JTAG access to the scan chains see Figure 6 14 Figure 6 14 Debug Subsystem Block Diagram 6 20 2 Debug Components Memory Map Table 6 33 Debug Components Memory Map MODULE NAME FRAME...

Page 89: ...fications Copyright 2013 2016 Texas Instruments Incorporated 6 20 4 Debug ROM The Debug ROM stores the location of the components on the Debug APB bus see Table 6 35 Table 6 35 Debug ROM Table ADDRESS...

Page 90: ...m of 50 pF load on TDO 6 20 5 JTAG Scan Interface Timings Table 6 36 JTAG Scan Interface Timing 1 NO PARAMETER MIN MAX UNIT fTCK TCK frequency at HCLKmax 12 MHz fRTCK RTCK frequency at TCKmax and HCLK...

Page 91: ...tie offs The output of this combinational logic is compared against a secret hard wired 128 bit value A match results in the UNLOCK signal being asserted so that the device is now unsecure A user can...

Page 92: ...mation and Electrical Specifications Copyright 2013 2016 Texas Instruments Incorporated 6 20 7 Boundary Scan Chain The device supports BSDL compliant boundary scan for testing pin to pin compatibility...

Page 93: ...IN MAX UNIT tpw Input minimum pulse width tc VCLK 10 2 ns tin_slew Time for input signal to go from VIL to VIH or from VIH to VIL 1 ns 7 1 2 Output Timings Table 7 2 Switching Characteristics for Outp...

Page 94: ...CL 15 pF 2 5 CL 50 pF 4 CL 100 pF 7 2 CL 150 pF 12 5 Rise time tr 2mA z mode CL 15 pF 8 CL 50 pF 15 CL 100 pF 23 CL 150 pF 33 Fall time tf CL 15 pF 8 CL 50 pF 15 CL 100 pF 23 CL 150 pF 33 1 This spec...

Page 95: ...if the output voltage is above VREFHIGH then the output buffer impedance will again increase to Hi Z A high degree of decoupling between internal power bus ad output pin will occur with capacitive loa...

Page 96: ...VIM ADC Wrapper VIM EQEP1 EQEP2 CPU System Module VIM ADC Wrapper VIM EQEP1 EQEP2 CPU System Module VIM Mux Selector Mux Selector EQEP1ERR EQEP2ERR EQEP1ERR or EQEP2ERR EQEP1ERR EQEP2ERR EQEP1ERR or E...

Page 97: ...0714 www ti com SPNS226E JUNE 2013 REVISED NOVEMBER 2016 Submit Documentation Feedback Product Folder Links TMS570LS0714 Peripheral Information and Electrical Specifications Copyright 2013 2016 Texas...

Page 98: ...ault value of the control registers to enable the clocks to the ePWMx modules is 1 This means that the VCLK4 clock connections to the ePWMx modules are enabled by default The application can choose to...

Page 99: ...re the prescaler values and desired ePWM modes 4 Configure TBCLKSYNC 1 7 2 5 ePWM Synchronization with External Devices The output sync from the ePWM1 module is also exported to a device output termin...

Page 100: ...PINMMR42 10 8 001 PINMMR42 10 8 010 PINMMR42 10 8 100 ePWM7 PINMMR42 18 16 001 PINMMR42 18 16 010 PINMMR42 18 16 100 7 2 6 3 Trip Zone TZ5n This trip zone input is dedicated to a clock failure on the...

Page 101: ...ePWMx Switching Characteristics PARAMETER TEST CONDITIONS MIN MAX UNIT tw PWM Pulse duration ePWMx output high or low 33 33 ns tw SYNCOUT Synchronization Output Pulse Width 8 tc VCLK4 cycles td PWM t...

Page 102: ...ck Product Folder Links TMS570LS0714 Peripheral Information and Electrical Specifications Copyright 2013 2016 Texas Instruments Incorporated 7 3 Enhanced Capture Modules eCAP Figure 7 6 shows how the...

Page 103: ...registers to enable the clocks to the eCAPx modules is 1 This means that the VCLK4 clock connections to the eCAPx modules are enabled by default The application can choose to gate off the VCLK4 clock...

Page 104: ...corporated 1 The filter width is 6 VCLK4 cycles 7 3 4 Enhanced Capture Module eCAP Electrical Data Timing Table 7 13 eCAPx Timing Requirements TEST CONDITIONS MIN MAX UNIT tw CAP Pulse width capture i...

Page 105: ...zation selection of the EQEPxA B pins to each eQEPx module see Figure 7 9 Figure 7 8 eQEP Module Interconnections Figure 7 9 shows the detailed input synchronization selection asynchronous double sync...

Page 106: ...le VCLK4 synchronized and filtered input as shown in Table 7 16 Table 7 16 Device Level Input Connection to eQEPx Modules INPUT SIGNAL CONTROL FOR DOUBLE SYNCHRONIZED CONNECTION TO eQEPx CONTROL FOR D...

Page 107: ...ripheral Information and Electrical Specifications Copyright 2013 2016 Texas Instruments Incorporated Table 7 18 eQEPx Switching Characteristics PARAMETER MIN MAX UNIT td CNTR xin Delay time external...

Page 108: ...K One memory region per conversion group is available Event Group Group 1 and Group 2 Allocation of channels to conversion groups is completely programmable Supports flexible channel conversion order...

Page 109: ...PINMMR30 1 1 OPTION A CONTROL FOR OPTION A OPTION B CONTROL FOR OPTION B 000 1 AD1EVT AD1EVT AD1EVT 001 2 N2HET1 8 N2HET2 5 PINMMR30 8 1 ePWM_B PINMMR30 8 0 and PINMMR30 9 1 010 3 N2HET1 10 N2HET1 27...

Page 110: ...ionality instead of the ADEVT N2HET1 x or GIOB x signals then care must be taken to disable these signals from triggering conversions there is no multiplexing on the input connections If ePWM_B ePWM_A...

Page 111: ...PINMMR30 1 1 OPTION A CONTROL FOR OPTION A OPTION B CONTROL FOR OPTION B 000 1 AD2EVT AD2EVT AD2EVT 001 2 N2HET1 8 N2HET2 5 PINMMR31 16 1 ePWM_B PINMMR31 16 0 and PINMMR31 17 1 010 3 N2HET1 10 N2HET1...

Page 112: ...hese signals from triggering conversions there is no multiplexing on the input connections If ePWM_B ePWM_A2 ePWM_AB N2HET2 1 N2HET2 5 N2HET2 13 N2HET1 11 N2HET1 17 or N2HET1 19 is used to trigger the...

Page 113: ...A EPWM7SOCB EPWM7 module ePWM_B ePWM_A1 ePWM_A2 ePWM_AB SOCAEN SOCBEN bits inside ePWMx modules Controlled by PINMMR 113 TMS570LS0714 www ti com SPNS226E JUNE 2013 REVISED NOVEMBER 2016 Submit Documen...

Page 114: ...tch is implemented by using the control registers in the PINMMR module Figure 7 11 shows an example of the implementation for the switch on SOC1A The switches on the other SOCA signals are implemented...

Page 115: ...igure 7 12 250 Rsamp ADC sample switch on resistance See Figure 7 12 250 Cmux Input mux capacitance See Figure 7 12 16 pF Csamp ADC sample capacitance See Figure 7 12 13 pF IAIL Analog off state input...

Page 116: ...SAMP register for each conversion group The sample time must be determined by accounting for the external impedance connected to the input channel as well as the internal impedance of the ADC 3 This i...

Page 117: ...ference between the first ideal transition from code 000h to 001h and the actual transition 10 bit mode 1 LSB 12 bit mode 2 FSET Full Scale Offset Difference between the range of the measured code tra...

Page 118: ...Product Folder Links TMS570LS0714 Peripheral Information and Electrical Specifications Copyright 2013 2016 Texas Instruments Incorporated 7 5 4 Performance Accuracy Specifications 7 5 4 1 MibADC Nonli...

Page 119: ...E JUNE 2013 REVISED NOVEMBER 2016 Submit Documentation Feedback Product Folder Links TMS570LS0714 Peripheral Information and Electrical Specifications Copyright 2013 2016 Texas Instruments Incorporate...

Page 120: ...ti com Submit Documentation Feedback Product Folder Links TMS570LS0714 Peripheral Information and Electrical Specifications Copyright 2013 2016 Texas Instruments Incorporated 7 5 4 2 MibADC Total Erro...

Page 121: ...llowing features Each I O pin can be configured as Input Output Open drain The interrupts have the following characteristics Programmable interrupt detection either on both edges or on a single edge s...

Page 122: ...r dedicated time and angle functions 160 words of instruction RAM protected by parity User defined number of 25 bit virtual counters for timer event counters and angle counters 7 bit hardware counters...

Page 123: ...25 HRP LRP tc VCLK2 2 ns 7 7 4 N2HET1 to N2HET2 Synchronization In some applications the N2HET resolutions must be synchronized Some other applications require a single time base to be used for all PW...

Page 124: ...th N2HET1 31 and N2HET2 0 can be configured to be internal only channels That is the connection to the DCC module is made directly from the output of the N2HETx module from the input of the output buf...

Page 125: ...8 or 16 byte and system memory address fixed 32 or 64 bit One shot circular and auto switch buffer transfer modes Request lost detection 7 7 7 2 Trigger Connections For the transfer request line trig...

Page 126: ...g 7 8 1 Features Features of the DCAN module include Supports CAN protocol version 2 0 part A B Bit rates up to 1 Mbps The CAN kernel can be clocked by the oscillator for baud rate generation 64 mailb...

Page 127: ...gh an RS 232 port or over a K line The LIN standard is based on the SCI Universal Asynchronous Receiver Transmitter UART serial data link format The communication concept is single master multiple sla...

Page 128: ...sed on the following Data word length programmable from 1 to 8 bits Additional address bit in address bit mode Parity programmable for 0 or 1 parity bit odd or even parity Stop programmable for 1 or 2...

Page 129: ...1 Bit or Byte format transfer 7 and 10 bit device addressing modes General call START byte Multimaster transmitter or slave receiver mode Multimaster receiver or slave transmitter mode Combined master...

Page 130: ...Table 7 31 I2C Signals SDA and SCL Switching Characteristics 1 PARAMETER STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX tc I2CCLK Cycle time internal module clock for I2C prescaled from VCLK 75 2 149 7...

Page 131: ...device does not stretch the low period tw SCLL of the SCL signal A Fast mode I2C bus device can be used in a Standard mode I2C bus system but the requirement tsu SDA SCLH 250 ns must then be met This...

Page 132: ...MibSPIx SPIx I Os MibSPI1 MIBSPI1SIMO 1 0 MIBSPI1SOMI 1 0 MIBSPI1CLK MIBSPI1nCS 5 4 2 0 MIBSPI1nENA MibSPI3 MIBSPI3SIMO MIBSPI3SOMI MIBSPI3CLK MIBSPI3nCS 5 0 MIBSPI3nENA MibSPI5 MIBSPI5SIMO 0 MIBSPI5S...

Page 133: ...N2HET1 18 EVENT14 1111 Intern Tick counter NOTE For N2HET1 trigger sources the connection to the MibSPI1 module trigger input is made from the input side of the output buffer at the N2HET1 module bou...

Page 134: ...N2HET1 18 EVENT14 1111 Intern Tick counter NOTE For N2HET1 trigger sources the connection to the MibSPI3 module trigger input is made from the input side of the output buffer at the N2HET1 module bou...

Page 135: ...N2HET1 18 EVENT14 1111 Intern Tick counter NOTE For N2HET1 trigger sources the connection to the MibSPI5 module trigger input is made from the input side of the output buffer at the N2HET1 module bou...

Page 136: ...SIMO valid before SPICLK low clock polarity 0 0 5tc SPC M 6 ns td SPCL SIMO M Delay time SPISIMO valid before SPICLK high clock polarity 1 0 5tc SPC M 6 5 5 tv SPCL SIMO M Valid time SPISIMO data vali...

Page 137: ...Be Valid Master Out Data Is Valid 3 2 1 5 4 6 6 7 137 TMS570LS0714 www ti com SPNS226E JUNE 2013 REVISED NOVEMBER 2016 Submit Documentation Feedback Product Folder Links TMS570LS0714 Peripheral Inform...

Page 138: ...3 4 5 tv SIMO SPCH M Valid time SPICLK high after SPISIMO data valid clock polarity 0 0 5tc SPC M 6 ns tv SIMO SPCL M Valid time SPICLK low after SPISIMO data valid clock polarity 1 0 5tc SPC M 6 5 5...

Page 139: ...ct Folder Links TMS570LS0714 Peripheral Information and Electrical Specifications Copyright 2013 2016 Texas Instruments Incorporated Table 7 37 SPI Master Mode External Timing Parameters CLOCK PHASE 1...

Page 140: ...s 2 6 tw SPCH S Pulse duration SPICLK high clock polarity 0 14 ns tw SPCL S Pulse duration SPICLK low clock polarity 1 14 3 6 tw SPCL S Pulse duration SPICLK low clock polarity 0 14 ns tw SPCH S Pulse...

Page 141: ...a Is Valid 6 6 6 SPISIMO 141 TMS570LS0714 www ti com SPNS226E JUNE 2013 REVISED NOVEMBER 2016 Submit Documentation Feedback Product Folder Links TMS570LS0714 Peripheral Information and Electrical Spec...

Page 142: ...SPICLK low clock polarity 1 14 3 6 tw SPCL S Pulse duration SPICLK low clock polarity 0 14 ns tw SPCH S Pulse duration SPICLK high clock polarity 1 14 4 6 td SOMI SPCL S Delay time SPISOMI data valid...

Page 143: ...olarity 1 SPICLK clock polarity 0 3 2 1 4 143 TMS570LS0714 www ti com SPNS226E JUNE 2013 REVISED NOVEMBER 2016 Submit Documentation Feedback Product Folder Links TMS570LS0714 Peripheral Information an...

Page 144: ...accuracy or completeness TI s customers are responsible for determining suitability of components for their purposes Customers should validate and test their design implementation to confirm system f...

Page 145: ...and Development Support Tool Nomenclature To designate the stages in the product development cycle TI assigns prefixes to the part numbers of all devices and support tools Each commercial family membe...

Page 146: ...Quad Flatpack PZ 100 Pin Plastic Quad Flatpack Temperature Range Q 40o C to 125o C Quality Designator Q1 Automotive Shipping Options R Tape and Reel Full Part TMS 570 LS 07 1 4 A PGE Q Q1 R Orderable...

Page 147: ...features of the Hercules MCU platform For additional software downloads and other resources visit the Hercules LaunchPads wiki 9 3 2 Development Tools Development tools includes both hardware and soft...

Page 148: ...generate driver code which can be easily imported into integrated development environments like CCS IDE IAR Workbench etc The HALCoGen tool also includes several example projects SafeTI HALCoGen Comp...

Page 149: ...Linked contents are provided AS IS by the respective contributors They do not constitute TI specifications and do not necessarily reflect TI s views see TI s Terms of Use TI E2E Online Community The T...

Page 150: ...truments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtl...

Page 151: ...d Write R Read only n value after reset Table 9 1 Device ID Bit Allocation Register Field Descriptions BIT FIELD VALUE DESCRIPTION 31 CP15 Indicates the presence of coprocessor 15 1 CP15 present 30 17...

Page 152: ...Submit Documentation Feedback Product Folder Links TMS570LS0714 Device and Documentation Support Copyright 2013 2016 Texas Instruments Incorporated 9 10 Module Certifications The following communicat...

Page 153: ...JUNE 2013 REVISED NOVEMBER 2016 Submit Documentation Feedback Product Folder Links TMS570LS0714 Device and Documentation Support Copyright 2013 2016 Texas Instruments Incorporated 9 10 1 DCAN Certifi...

Page 154: ...016 www ti com Submit Documentation Feedback Product Folder Links TMS570LS0714 Device and Documentation Support Copyright 2013 2016 Texas Instruments Incorporated 9 10 2 LIN Certification 9 10 2 1 LIN...

Page 155: ...OVEMBER 2016 Submit Documentation Feedback Product Folder Links TMS570LS0714 Device and Documentation Support Copyright 2013 2016 Texas Instruments Incorporated 9 10 2 2 LIN Slave Mode Fixed Baud Rate...

Page 156: ...ww ti com Submit Documentation Feedback Product Folder Links TMS570LS0714 Device and Documentation Support Copyright 2013 2016 Texas Instruments Incorporated 9 10 2 3 LIN Slave Mode Adaptive Baud Rate...

Page 157: ...ents Incorporated 10 Mechanical Packaging and Orderable Information 10 1 Packaging Information The following pages include mechanical packaging and orderable information This information is the most c...

Page 158: ...sed between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI de...

Page 159: ...M www ti com 17 Mar 2016 Addendum Page 2 In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Custo...

Page 160: ...AD FLATPACK 4040147 C 10 96 0 27 72 0 17 37 73 0 13 NOM 0 25 0 75 0 45 0 05 MIN 36 Seating Plane Gage Plane 108 109 144 SQ SQ 22 20 21 80 1 19 80 17 50 TYP 20 20 1 35 1 45 1 60 MAX M 0 08 0 7 0 08 0 5...

Page 161: ...UAD FLATPACK 4040149 B 11 96 50 26 0 13 NOM Gage Plane 0 25 0 45 0 75 0 05 MIN 0 27 51 25 75 1 12 00 TYP 0 17 76 100 SQ SQ 15 80 16 20 13 80 1 35 1 45 1 60 MAX 14 20 0 7 Seating Plane 0 08 0 50 M 0 08...

Page 162: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

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