![background image](http://html1.mh-extra.com/html/texas-instruments/tms380c26/tms380c26_user-manual_1097041067.webp)
TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
67
PARAMETER MEASUREMENT INFORMATION
80x8x mode bus arbitration timing, SIF takes control
NO.
PARAMETER
MIN
MAX
UNIT
208a
Setup of asynchronous signal SBBSY and SHLDA before SBCLK no longer high to guarantee
recognition on that cycle
15
ns
208b
Hold of asynchronous signal SBBSY and SHLDA after SBCLK low to guarantee recognition on
that cycle
15
ns
212
Delay from SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid
25
ns
224a
Delay from SBCLK low in cycle I2 to SOWN low
25
ns
224c
Delay from SBCLK low in cycle I2 to SDDIR low in DMA read
30
ns
230
Delay from SBCLK high to SHRQ high
25
ns
241
Delay from SBCLK high in TX cycle to SRD and SWR high, bus acquisition
25
ns
241a†
Hold of SRD and SWR high-impedance after SOWN low, bus acquisition
tc(SCK) – 15
ns
† This specification has been characterized to meet stated value.