TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
52
PARAMETER MEASUREMENT INFORMATION
memory bus timing: DRAM refresh timing
t
M
is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)
NO.
PARAMETER
MIN
MAX
UNIT
15
Setup time of row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer
high
1.5tM –11.5
ns
16
Hold time of row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high
tM – 6.5
ns
18
Pulse duration of MRAS low
4.5tM – 9
ns
19
Pulse duration of MRAS high
3.5tM – 9
ns
73a
Setup time of MCAS low before MRAS no longer high
1.5tM –11.5
ns
73b
Hold time of MCAS low after MRAS low
4.5tM – 6.5
ns
73c
Setup time of MREF high before MCAS no longer high
tM –14
ns
73d
Hold time of MREF high after MCAS high
tM –9
ns
MREF
MCAS
MRAS
MADL0–MADL7
Address
Address
Refresh
73c
73d
73b
73a
19
18
16
15
Figure 17. Memory Bus Timing: DRAM Refresh Cycle
