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TMS380C26

NETWORK COMMPROCESSOR

SPWS010A–APRIL 1992–REVISED MARCH 1993

POST OFFICE BOX 1443

•

HOUSTON, TEXAS

77251–1443

PARAMETER MEASUREMENT INFORMATION

75a
74a

MBCLK1

MBCLK2

MBEN

MDDIR

MAL

MBIAEN

MBRQ

MBGR

Figure 12. Memory Bus Timing: TMS380C26 Releases Control of Bus (continued)

Summary of Contents for TMS380C26

Page 1: ...Second High Speed Bus Master DMA Interface Low Cost Host Slave I O Interface Option Up to 32 Bit Host Address Bus Selectable Host System Bus Options 80x8x or 68xxx Type Bus and Memory Organization 8...

Page 2: ...DL3 VDD5 SSL V 17 DD4 V NMI 16 15 EXTINT0 14 EXTINT1 13 EXTINT2 12 EXTINT3 11 MADL0 10 MADL1 9 MADL2 8 MADL3 7 MADL4 6 MADL5 5 MADL6 4 MADL7 3 MAXPL 2 SS4 V 1 MBGR 132 MBGQ 131 MAXPH 130 MADH0 129 MAD...

Page 3: ...imizing the frequency of host LAN subsystem communications by allowing larger blocks of information to be transferred at one time The support of large local memory is important in applications that re...

Page 4: ...SADL7 SPH SPL SBRLS SINTR SIRQ SDDIR SDBEN SALE SXAL SOWN SIACK SBCLK SRD SUDS SWR SLDS SRDY SDTACK SI M SHLDA SBGR SBHE SRNW SRAS SAS S8 SHALT SRESET SRS0 SRS1 SRS2 SBERR SCS SRSX SHRQ SBRQ NSELOUT0...

Page 5: ...10 9 8 7 6 5 4 3 I O Local Memory Address Data and Status Bus low byte For the first quarter of the local memory cycle these bus lines carry address bits A7 to A14 for the second quarter they carry a...

Page 6: ...th MDDIR which selects the buffer output direction H Buffer output disabled L Buffer output enabled MBGR 132 OUT Reserved Must be left unconnected MBIAEN 101 OUT Burned In Address Enable This is an ou...

Page 7: ...sed to provide a chip select for ROMs when the BOOT bit of the SIFACL register is zero i e when code is resident in ROM not RAM It can be latched by MAL It goes low for any read from addresses 00 0010...

Page 8: ...parity checking for the local memory H Local memory data bus checked for parity see Note 1 L Local memory data bus NOT checked for parity NSELOUT0 NSELOUT1 21 93 OUT OUT Network Selection Outputs The...

Page 9: ...in during arbitration The sample has one of 2 two values see Note 1 H Not busy The TMS380C26 may become Bus Master if the grant condition is met L Busy The TMS380C26 cannot become Bus Master SBCLK 44...

Page 10: ...signal is from the host processor to acknowledge the interrupt request from the TMS380C26 H System interrupt not acknowledged see Note 1 L System interrupt acknowledged the TMS380C26 places its inter...

Page 11: ...DIO and an input otherwise H System bus NOT ready L Data transfer is complete system bus is ready SRESET 25 IN System Reset This input signal is activated to place the TMS380C26 into a known initial...

Page 12: ...ft unconnected see Note 1 S8 SHALT 32 IN System 8 16 bit bus select This pin selects the bus width used for communications through the system interface On the rising edge of SRESET the TMS380C26 latch...

Page 13: ...C26 samples the value on this pin during arbitration The sample has one of 2 two values see Note 1 H Not busy The TMS380C26 may become Bus Master if the grant condition is met L Busy The TMS380C26 can...

Page 14: ...tem interrupt acknowledged the TMS380C26 places its interrupt vector onto the system bus SI M 35 IN System Intel Motorola Mode Select The value on this pin specifies the system interface mode H Intel...

Page 15: ...to the bus error signal of the 68000 microprocessor It is internally synchronized to SBCLK This input is driven low during a DMA cycle to indicate to the TMS380C26 that the cycle must be terminated Se...

Page 16: ...eed this input must be supplied a 32 MHz signal At 4 Mbps ring speed the input signal must be 8 MHz and may be the output from the OSCOUT pin RCLK RXC 94 IN Ring Interface Recovered Clock see Note 5 T...

Page 17: ...his clock in a low phase It is normally connectedto the RXC output pin of an Ethernet Serial Network Interface SNI chip The TMS380C26 requires this pin to be maintained in the low state when CRS is no...

Page 18: ...en CAF mode is enabled See table given below in XMATCH pin description see Note 1 H No address match by external address checker L External address checker armed state XMATCH 81 IN External Match sign...

Page 19: ...51 1443 19 Terminal Functions continued PIN NAME NO I O DESCRIPTION VSSL 17 83 IN Groundreferencefordigitallogic AllVSSpinsmustbeattachedtothecommonsystemgroundplane VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 91 1...

Page 20: ...ata using any of these three methods Direct Memory Access DMA Direct Input Output DIO or Pseudo Direct Memory Access PDMA DMA or PDMA is used to transfer all data to from host memory from to local mem...

Page 21: ...Bytes in local memory Hardware in the MIF allows the TMS380C26 to be directly connected to DRAMs without additional circuitry This glueless DRAM connection includes the DRAM refresh controller The MIF...

Page 22: ...RC detection of network data violations and parity on internal data paths All data paths and registers are optionally parity protected to assure functional integrity adapter support function ASF The A...

Page 23: ...e Pointer 28 source address of the last received frame Pointer 34 last beacon type Pointer 36 last major vector Pointer 38 ring status Pointer 40 soft error timer value Pointer 42 ring interface error...

Page 24: ...1 Pointer 0 node address Pointer 6 group address Pointer 10 functional address 01 0A08 Pointer to MAC buffer a special buffer used by the software to transmit adapter generated MAC frames in chapter...

Page 25: ...0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 SIFDAT LSB SIFDAT MSB SIFDAT INC LSB SIFDAT INC MSB SIFADR LSB SIFADR MSB SIF...

Page 26: ...on If the network speed and type are software configurable these bits can be used to determine which configurations are supported by the network hardware TEST0 TEST1 TEST2 Description L L H Reserved L...

Page 27: ...TMS380C26 This bit has the same effect as the SRESET pin except that the DIO interface to the SIFACL register is maintained This bit will be set to one if a clock failure is detected OSCIN PXTALIN RC...

Page 28: ...upt 0 X X 0 X The TMS380C26 can not generate a system interrupt The value on the SHLDA SBGR pin is ignored Bit 13 PEN Adapter Parity Enable This bit determines whether data transfers within the TMS380...

Page 29: ...e use of five bits in the SIFACL register The logic model for the SIFACL register control of pseudo DMA operation is shown in Figure 3 Motorola Mode Internal Signals Host Interface SYSTEM_INTERRUPT SI...

Page 30: ...result of the manufacturing test environment This signal has been characterized to a minimum level of 2 4 V over the full temperature range The maximum level specified is a result of the manufacturin...

Page 31: ...gh transition the level at which the signal is said to be no longer low is 0 8 volts and the level at which the signal is said to be high is 2 volts as shown below The rise and fall times are not spec...

Page 32: ...N OSCIN OSCOUT MBCLK1 MBCLK2 4 Periods 8 Periods 12 Periods 16 Periods 20 Periods When CLKDIV 1 Reference The MBCLK1 and MBCLK2 signals have no timing relationship to the OSCOUT signal The MBCLK1 and...

Page 33: ...ootstrap mode RAM ROM PRTYEN Default parity select enabled disabled TEST0 Test pin indicates network type TEST1 Test pin indicates network type TEST2 Test pin indicates network type TEST3 Test pin for...

Page 34: ...6 500 ns 108 tw OSCH Pulse duration of OSCIN high 5 5 ns 109 tw OSCL Pulse duration of OSCIN low 5 5 ns 110 tt OSC Transition time of OSCIN 3 ns 111 td OSCV CKV Delay time from OSCIN valid to MBCLK1...

Page 35: ...CLK2 MBCLK1 OSCIN SBCLK VDD 288 289 119 110 109 110 108 107 106 106 100 Minimun VDD High Level 104 105 103 102 101 117 118 111 NOTE A In order to represent the information on one figure non actual pha...

Page 36: ...ns 8 Setup time of address enable on MAX0 MAX2 and MROMEN before MBCLK1 no longer high tM 9 ns 9 Setup time of row address on MADL0 MADL7 MAXPH and MAXPL before MBCLK1 no longer high tM 14 ns 10 Setu...

Page 37: ...METER MEASUREMENT INFORMATION MAL MAXPH MAXPL MADL0 MADL7 MAX0 MAX2 MROMEN MBCLK2 MBCLK1 Address Col Row Address ADD EN 11 10 9 8 14 13 12 2 3 1 2 1 7 6 5 4 MADH0 MADH7 NMI MRESET 120 121 126 Status 1...

Page 38: ...MAXPL and status MADH0 MADH7 before MCAS no longer high 0 5tM 9 ns 21 Hold time of column address MADL0 MADL7 MAXPH and MAXPL and status MADH0 MADH7 after MCAS low tM 9 ns 22 Hold time of column addre...

Page 39: ...77251 1443 39 PARAMETER MEASUREMENT INFORMATION MADH0 MADH7 MAX0 MAX2 MROMEN MAL MCAS MRAS MAXPH MAXPL MADL0 MADL7 Row Column Column Row Address Status Status Address Address ADD EN 31 30 28 29 24 26...

Page 40: ...MAXPL MADH0 MADH7 and MADL0 MADL7 after MOE high see Note 13 2tM 15 ns 48 Setup time of address status high impedance on MAXPH MAXPL MADL0 MADL7 and MADH0 MADH7 before MBEN no longer high 0 ns 48a Set...

Page 41: ...41 PARAMETER MEASUREMENT INFORMATION MDDIR MBEN MBIAEN MOE MCAS MRAS MAXPH MAXPL MADH0 MADH7 MADL0 MADL7 MAX0 MAX2 MROMEN Address Enable Address Address Status Address Address Data Parity 53 54 55 51...

Page 42: ...up time of valid data parity before MW no longer high 0 5tM 11 5 ns 64 Pulse duration of MW low 2 5tM 9 ns 65 Hold time of data parity out valid after MW high 0 5tM 10 5 ns 66 Setup time of address va...

Page 43: ...E BOX 1443 HOUSTON TEXAS 77251 1443 43 PARAMETER MEASUREMENT INFORMATION Data Parity Out ADD STS Address Address Enable Address MDDIR MBEN MW MCAS MRAS MAXPH MAXPL MADH0 MADH7 MADL0 MADL7 MAX0 MAX2 MR...

Page 44: ...of MBEN valid after MBCLK1 rising edge bus release tM 13 ns 75 Delay time from MBCLK1 high to MIF output high impedance bus release 0 5tM ns 75a Delay time from MBCLK1 high to MBEN output high impeda...

Page 45: ...EVISED MARCH 1993 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 45 PARAMETER MEASUREMENT INFORMATION 78 77 76 75a 74a 75 74 75 74 75 74 MBCLK1 MBCLK2 MBEN MDDIR MAL MBIAEN MBRQ MBGR Figure 12 Memory B...

Page 46: ...eighth of a local memory cycle 31 25 ns minimum NO PARAMETER MIN MAX UNIT 79 Hold time of MIF output high impedance after MBCKL1 rising edge bus resume tM 13 ns 80 Delay time from MBCLK1 high to MIF o...

Page 47: ...H 1993 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 47 PARAMETER MEASUREMENT INFORMATION 80 79 80 79 80 79 80 79 80 79 80 79 MBCLK1 MAX0 MAX2 MOROMEN MAXPH MAXPL MADH0 MADH7 MADL0 MADL7 MRAS MCAS MW...

Page 48: ...REVISED MARCH 1993 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 48 PARAMETER MEASUREMENT INFORMATION 83 81 82 80 79 MBCLK1 MBCLK2 MBEN MDDIR MAL MBIAEN MBRQ MBGR 80 79 80 79 80 79 Figure 14 Memory Bu...

Page 49: ...address after MBCLK1 low external bus master access 0 ns 88 Setup time of address high impedance before MBCLK1 falling edge external bus master read 0 ns 89 Setup time of data parity valid before MBCL...

Page 50: ...HOUSTON TEXAS 77251 1443 50 PARAMETER MEASUREMENT INFORMATION 84 MBCLK1 MBCLK2 MAX0 MAX2 85 88 MAXPH MAXPL MADH0 MADH7 MADL0 MADL7 Address In Data Parity Address In Address In MDDIR MACS 86 87 Address...

Page 51: ...lling edge external bus master write 21 ns 97 Hold time of valid data parity after MBCLK2 low external bus master write 0 ns 98 Setup time of MDDIR high before MBCLK2 falling edge external bus master...

Page 52: ...longer high 1 5tM 11 5 ns 16 Hold time of row address on MADL0 MADL7 MAXPH and MAXPL after MRAS no longer high tM 6 5 ns 18 Pulse duration of MRAS low 4 5tM 9 ns 19 Pulse duration of MRAS high 3 5tM...

Page 53: ...MENT INFORMATION XMATCH and XFAIL timing tM is the cycle time of one eighth of a local memory cycle 31 25 ns minimum NO PARAMETER MIN MAX UNIT 127 Delay from status bit 7 high to XMATCH and XFAIL reco...

Page 54: ...55 Setup of RCVR valid before rising edge 1 8 V of RCLK at 16 Mbps 10 ns 156 Hold of RCVR valid after rising edge 1 8 V of RCLK at 16 Mbps 4 ns 158L Pulse duration of ring baud clock low 4 Mbps 40 ns...

Page 55: ...V to DRVR falling edge 1 0 V see Note 15 162 Delay from RCLK or PXTALIN falling edge 1 0 V to DRVR falling edge 1 0 V see Note 15 163 Delay from RCLK or PXTALIN falling edge 1 0 V to DRVR rising edge...

Page 56: ...duration of TXC 45 ns 301 CLKPER Cycle time of TXC 95 1000 ns TXC 300 2 4 V 0 45 V 300 301 Figure 21 Ethernet Timing Of Clock Signals ethernet timing of XMIT signals NO PARAMETER MIN TYP MAX UNIT 305...

Page 57: ...rnally recognized to first valid data sample see Notes 16 and 17 nominal 3 clk cycles 314 RXCHI Pulse duration of RXC high 36 ns 315 RXCL0 Pulse duration of RXC low 36 ns NOTES 16 For valid frame sync...

Page 58: ...20 ns 321 CRSHLD Hold time of CRS low after RXC no longer low to determine if last data bit seen on previous RXC no longer low 0 ns 322 XTRCYC Number of extra RXC clock cycles after last data bit CRS...

Page 59: ...ailure circuitry may become activated resetting the device CRS 1 RXC 330 Figure 25 Ethernet Timing of RCV Signals No RXC ethernet timing of XMIT signals NO PARAMETER MIN TYP MAX UNIT 340 HBWIN Delay t...

Page 60: ...mpled high TXC high to first transmitted JAM bit on TXD see Note 20 4 cycles 351 COLSET Setup of COLL high before TXC high 20 ns 352 COLPUL Minimum pulse duration of COLL high for guaranteed sample 20...

Page 61: ...WR and SIACK high from previous cycle to SRD no longer high 55 ns 273a Hold time of SRD SWR and SIACK high after SRD high 55 ns 275 Delay from SRD and SWR or SCS high to SRDY high see Note 21 35 ns 27...

Page 62: ...272a 272a 286 273a 273a 282R 279 259 When the TMS380C26 begins to drive SDBEN inactive it has already latched the write data internally Parameter 263 must be met to the input of the data buffers NOTES...

Page 63: ...U005 subsection 3 4 1 1 1 275 Delay from SWR or SCS high to SRDY high see Note 21 35 ns 279 Delay from SWR high to SRDY high impedance 65 ns 280 Delay from SWR low to SDDIR low see Note 21 25 ns 281 D...

Page 64: ...SRAS SCS SRSX SRS0 SRS2 SBHE 262 276 267 266a 256 265 HI Z HI Z HI Z HI Z 281a 282b 275 272a 282W 283W Data 255 272a 272a 273a 286 273a 273a 281 279 263 280 268 264 When the TMS380C26 begins to drive...

Page 65: ...61 Delay from SIACK high to SAD high impedance see Note 21 35 ns 261a Hold of output data valid after SIACK high see Note 21 0 ns 272a Setup of inactive data strobe high to SIACK no longer high 55 ns...

Page 66: ...SCS SRSX SRS0 SRS2 SBHE Only SCS needs to be inactive All others are Don t Care High HI Z HI Z HI Z Output Data Valid 261 261a 260 259 275 279 283R 282a HI Z 276 255 273a 273a 273a 272a 272a 272a 282R...

Page 67: ...synchronous signal SBBSY and SHLDA after SBCLK low to guarantee recognition on that cycle 15 ns 212 Delay from SBCLK low to SADH0 SADH7 SADL0 SADL7 SPH and SPL valid 25 ns 224a Delay from SBCLK low in...

Page 68: ...DH0 SADH7 SADL0 SADL7 SPH SPL SBHE SRD SWR SHRQ SIF Outputs SBBSY SHLDA SBCLK SIF Inputs SIF Master Bus Exchange User Master T1 TX I2 I1 T4 Read Write Address Valid 212 212 241a 241 208b 208a 230 224c...

Page 69: ...ns 215 Pulse duration SALE and SXAL high tc SCK 25 ns 216 Delay from SBCLK high to SALE or SXAL high 25 ns 216a Hold of SALE or SXAL low after SRD high tw SCKL 15 ns 217 Delay from SBCLK high to SXAL...

Page 70: ...7 208a 208b 225R 229 237R 215 216 217 216 V TWAIT T1 T4 T3 T1 TX T4 HI Z 215 207b 216a 233 218 206 T2 If parameter 208A is not met then valid data must be present before SRDY goes low NOTES A Motorola...

Page 71: ...5 ns 216a Hold of SALE or SXAL low after SWR high tw SCKL 15 ns 217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 ns 218 Hold of address valid after SALE SXAL low tw...

Page 72: ...4 208b 208a 216a 225WH 223W 219 212 212 233 216 215 232 216 215 217 217 212 Output Data Address Valid HIGH HIGH 225W 237W 221 Extended Address 227W 218 233 NOTES A In 8 bit 80x8x mode SBHE SRNW is a d...

Page 73: ...nd SBHE high impedance before SOWN no longer low 0 ns This specification has been characterized to meet stated value READ WRITE SIF SIF SOWN see Note B SDDIR SADH0 SADH7 SADL0 SADL7 SPH SPL SBHE SRD S...

Page 74: ...ERETRY register is non zero the cycle will be retried If the BERETRY register is zero the System Interface will then release control of the system bus The System Interface ignores the assertion of SBE...

Page 75: ...SUDS or SLDS high to SDTACK high see Note 21 35 ns 276 Delay from SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately fol lowing access to the SIF 4000 ns 279 Delay...

Page 76: ...NT INFORMATION High Valid Output Data Valid SADH0 SADH7 SADL0 SADL7 SPH SPL SDTACK SDBEN SDDIR SUDS SLDS SRNW SIACK SCS SRSX SRS0 SRS1 260 282a 275 283R 273 268 272 HI Z HI Z HI Z HI Z 261 261a 267 25...

Page 77: ...o SDTACK high impedance 65 ns 280 Delay from SUDS or SLDS low to SDDIR low see Note 21 25 ns 281 Delay from SUDS or SLDS high to SDDIR high see Note 21 55 ns 281a Hold of SDDIR low after SUDS or SLDS...

Page 78: ...a 286 273a 279 SDTACK is an active low bus ready signal It must be asserted before data output When the TMS380C16 begins to drive SDBEN inactive it has already latched the write date internally Parame...

Page 79: ...strobe high 55 ns 275 Delay from SCS or SRNW high to SDTACK high see Note 21 35 ns 276 Delay from SDTACK low in the first DIO access to the SIF register to SDTACK low in the immediately following acc...

Page 80: ...DH7 SADL0 SADL7 SPH SPL see Note A SDTACK SDBEN SDDIR SLDS SRNW SIACK SCS SRSX SRS0 SRS1 SBHE 272a 275 261a 261 260 259 283R 267 HI Z HI Z HI Z 282a HI Z 276 255 282R 279 286 273a 286 SDTACK is an act...

Page 81: ...arantee recognition on this cycle 15 ns 212 Delay from SBCLK low to address valid 25 ns 224a Delay from SBCLK low in cycle I2 to SOWN low see Note 24 25 ns 224c Delay from SBCLK low in cycle I2 to SDD...

Page 82: ...tput WRITE READ SIF 230 224a 224c 212 208a 208b 241 241 208b 208a 230 READ WRITE HI Z Input 241a NOTES A In 80x8x mode the system interface deasserts SHRQ on the rising edge of SBCLK following the T4...

Page 83: ...LK low in T2 cycle to SAD high impedance 25 ns 215 Pulse duration SALE and SXAL high tc SCK 25 ns 216 Delay from SBCLK high to SALE or SXAL high 25 ns 216a Hold of SALE or SXAL low after SUDS and SAS...

Page 84: ...216 TWAIT V 233a 217 206 208a 208b 214 239 216 215 218 210 209 209 216a 229 218 239 237R 247 Extended Address 212 205 If parameter 208a is not met then valid data must be present before SDTACK goes l...

Page 85: ...ay from SBCLK high to SALE or SXAL high 25 ns 216a Hold of SALE or SXAL low after SUDS and SAS high tw SCKL 15 ns 217 Delay from SBCLK high to SXAL low in the TX cycle or SALE low in the T1 cycle 25 n...

Page 86: ...DS SLDS SAS SBCLK Output Data Address Extended Address 237W 208a 208b 225W 221 243 239 223W 219 209 216a 211 222 217 212 216 218 233 233 215 217 218 216 Low 215 212 225WH NOTES A All VSS pins should b...

Page 87: ...o SAD SPL SPH SUDS and SLDS high impedance bus release 35 ns 223b Delay from SBCLK low in I1 cycle to SBHE SRNW high impedance 45 ns 224b Delay from SBCLK low in cycle I2 to SOWN high 25 ns 224d Delay...

Page 88: ...ote A SIF Outputs SDTACK SBGR SBCLK SIF Inputs 230 220 224b 240 220 224d HI Z HI Z READ WRITE SIF WRITE READ 240 223b NOTE A In 80x8x mode the system interface deasserts SHRQ on the rising edge of SBC...

Page 89: ...ansfer is completed regardless of the value of SDTACK If the BERETRY register is non zero the cycle will be retried If the BERETRY register is zero the System Interface will then release control of th...

Page 90: ...normal completion with delayed start SBCLK T1 T W or 2 T3 T4 SDTACK SBERR SHALT TH T1 rerun cycle with delayed start SBCLK T1 T2 T3 T4 THB THE SDTACK SBERR SHALT T1 SOWN Only the relative placement o...

Page 91: ...ristics remain stable when the devices are operated in high humidity conditions The packages are intended for surface mounting on solder lands on 0 635 0 025 centers Leads require no additional cleani...

Page 92: ...ONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANT...

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