![background image](http://html1.mh-extra.com/html/texas-instruments/tms380c26/tms380c26_user-manual_1097041087.webp)
TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
87
PARAMETER MEASUREMENT INFORMATION
68xxx mode bus arbitration timing, SIF returns control
NO.
PARAMETER
MIN
MAX
UNIT
220†
Delay from SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS, and SLDS high-impedance, bus release
35
ns
223b†
Delay from SBCLK low in I1 cycle to SBHE/SRNW high-impedance
45
ns
224b
Delay from SBCLK low in cycle I2 to SOWN high
25
ns
224d
Delay from SBCLK low in cycle I2 to SDDIR high
30
ns
230
Delay from SBCLK high to either SHRQ low or SBRQ high
25
ns
240†
Setup of SUDS, SLDS, SRNW, and SAS control signals high-impedance before SOWN no longer low
0
ns
† This specification has been characterized to meet stated value.