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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL
1992–REVISED MARCH 1993
86
POST
OFFICE BOX 1443 HOUST
ON,
TEXAS
77001
•
PARAMETER MEASUREMENT INFORMATION
233a
211a
TWAIT
V
T1
T4
T3
T2
T1
TX
T4
SDBEN
SDDIR
SDTACK
(see Notes A and B)
SADL0–SADH7,
SADH0–SADL7,
SPL, SPH
SALE
SXAL
SRNW
SUDS,
SLDS
SAS
SBCLK
Output Data
Address
Extended Address
237W
208a
208b
225W
221
243
239
223W
219
209
216a
211
222
217
212
216
218
233
233
215
217
218
216
Low
215
212
225WH
NOTES: A. All VSS pins should be routed to minimize inductance to system ground.
B. On read cycle, read strobe remains active until the internal sample of incoming data is completed. Input-data may be removed when either the read strobe or SDBEN
becomes no longer active.
Figure 42. 68xxx Mode DMA Write Timing