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TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443
•
HOUSTON, TEXAS
77251–1443
37
PARAMETER MEASUREMENT INFORMATION
MAL
MAXPH,
MAXPL,
MADL0–MADL7
MAX0,
MAX2,
MROMEN
MBCLK2
MBCLK1
Address
Col
Row
Address
ADD/EN
11
10
9
8
14
13
12
2
3
1
2
1
7
6
5
4
MADH0–MADH7
NMI
MRESET
120
121
126
Status
129
tM
M4
M5
M6
M7
M8
M1
M1
M2
M3
M8
Valid
Valid
3
Figure 7. Memory Bus Timing: Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS