152
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016
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TMS320F28064 TMS320F28063 TMS320F28062
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
(1)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 6-79. STANDBY Mode Timing Requirements
MIN
MAX
UNIT
t
w(WAKE-
INT)
Pulse duration, external
wake-up signal
Without input qualification
3t
c(OSCCLK)
cycles
With input qualification
(1)
(2 + QUALSTDBY) * t
c(OSCCLK)
(1)
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
Table 6-80. STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t
d(IDLE-XCOL)
Delay time, IDLE instruction
executed to XCLKOUT low
32t
c(SCO)
45t
c(SCO)
cycles
t
d(WAKE-STBY)
Delay time, external wake signal to program execution
resume
(1)
cycles
•
Wake up from flash
–
Flash module in active state
Without input qualifier
100t
c(SCO)
cycles
With input qualifier
100t
c(SCO)
+ t
w(WAKE-INT)
•
Wake up from flash
–
Flash module in sleep state
Without input qualifier
1125t
c(SCO)
cycles
With input qualifier
1125t
c(SCO)
+ t
w(WAKE-INT)
•
Wake up from SARAM
Without input qualifier
100t
c(SCO)
cycles
With input qualifier
100t
c(SCO)
+ t
w(WAKE-INT)
