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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016
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TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
Detailed Description
Copyright © 2010–2016, Texas Instruments Incorporated
6.9.8
Inter-Integrated Circuit (I
2
C)
The device contains one I
2
C Serial Port.
Figure 6-47
shows how the I
2
C peripheral module interfaces
within the device.
The I
2
C module has the following features:
•
Compliance with the Philips Semiconductors I
2
C-bus specification (version 2.1):
–
Support for 1-bit to 8-bit format transfers
–
7-bit and 10-bit addressing modes
–
General call
–
START byte mode
–
Support for multiple master-transmitters and slave-receivers
–
Support for multiple slave-transmitters and master-receivers
–
Combined master transmit/receive and receive/transmit mode
–
Data transfer rate of from 10 kbps up to 400 kbps (I
2
C Fast-mode rate)
•
One 4-word receive FIFO and one 4-word transmit FIFO
•
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
Transmit-data ready
–
Receive-data ready
–
Register-access ready
–
No-acknowledgment received
–
Arbitration lost
–
Stop condition detected
–
Addressed as slave
•
An additional interrupt that can be used by the CPU when in FIFO mode
•
Module enable/disable capability
•
Free data format mode
